Display panel and display device with reduced charge accumulation in semiconductor layer

Patent metadata

Field	Value
Publication number	US-12094384-B2
Application number	US-202318204583-A
Country	US
Kind code	B2
Filing date	Jun 1, 2023
Priority date	Dec 29, 2020
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

A display panel has a display region and a frame region outside the display region. The display region includes a plurality of pixel circuits. The display panel includes a base substrate, a buffer layer, a semiconductor layer, a power signal layer, and an auxiliary circuit layer. The buffer layer is on a side of the base substrate. The buffer layer includes an a-Si layer. The semiconductor layer is on a side of the buffer layer away from the base substrate. The power signal layer is on a side of the semiconductor layer away from the base substrate. The power signal layer includes a plurality of first power voltage lines in the display region, and one first power voltage line of the plurality of first power voltage lines are electrically connected to a corresponding pixel circuit.

First claim

What is claimed is:

1. A display panel, having a display region and a frame region outside the display region wherein the display region includes a plurality of pixel circuits, the display panel comprising:
a base substrate;
a buffer layer on a side of the base substrate, wherein the buffer layer includes an a-Si layer;
a semiconductor layer on a side of the buffer layer away from the base substrate;
a power signal layer on a side of the semiconductor layer away from the base substrate, wherein the power signal layer includes a plurality of first power voltage lines in the display region, and one first power voltage line of the plurality of first power voltage lines are electrically connected to a corresponding pixel circuit of the plurality of pixel circuits; and
an auxiliary circuit layer arranged on a side of the a-Si layer away from the power signal layer and including a plurality of auxiliary electrode lines overlapping the plurality of first power voltage lines along a direction perpendicular to a plane of the display panel, to allow an electric field to be generated in an overlapped region of the auxiliary electrode lines and the first power voltage lines.

2. The display panel according to claim 1 , wherein the auxiliary circuit layer is connected to a fixed voltage.

3. The display panel according to claim 2 , wherein the fixed voltage is a negative voltage.

4. The display panel according to claim 1 , wherein:
the auxiliary circuit layer is electrically connected to a power signal terminal; and
the power signal terminal outputs a positive voltage signal and a negative voltage signal alternatively.

5. The display panel according to claim 4 , wherein:
an absolute voltage value of the negative voltage signal is greater than an absolute voltage value of the positive voltage signal.

6. The display panel according to claim 4 , wherein:
a time length of a single output of the negative voltage signal from the power signal terminal is less than or equal to 1 ms and greater than zero.

7. The display panel according to claim 4 , wherein:
a time length of a single output of the positive voltage signal and the negative voltage signal together by the power signal terminal is at least a time length of ¼ picture frame of the display panel.

8. The display panel according to claim 4 , wherein the plurality of first power voltage lines are electrically connected to the power signal terminal.

9. The display panel according to claim 8 , further comprising:
a second power voltage line in the display region and surrounding the plurality of first power voltage lines, wherein the second power voltage line is electrically connected to the power signal terminal.

10. The display panel according to claim 9 , wherein:
the second power voltage line also extends from the display region to the frame region.

11. The display panel according to claim 9 , wherein:
the frame region includes an encapsulation metal padding layer configured to surround the display region, and the second power voltage line is electrically connected to the encapsulation metal padding layer.

12. The display panel according to claim 8 , wherein:
the power signal terminal includes a first power supply line, a second power supply line, and a conversion circuit electrically connected to each of the first power supply line and the second power supply line; the first power supply line transmits the positive voltage signal, and the second power supply line transmits the negative voltage signal; and
the conversion circuit controls the first power supply line to be electrically connected to the power signal layer in a first stage and control the second power supply line to be electrically connected to the power signal layer in a second stage; and operations in the first stage and the second stage are alternately performed.

13. The display panel according to claim 12 , further comprising:
a cathode signal layer, electrically connected to the power signal terminal, wherein:
in the first stage, the conversion circuit controls the first power supply line to be electrically connected to the power signal layer and controls the second power supply line to be electrically connected to the cathode signal layer; and in the second stage, the conversion circuit controls the first power supply line to be electrically connected to the cathode signal layer and controls the second power supply line to be electrically connected to the power signal layer.

14. The display panel according to claim 13 , wherein:
the conversion circuit includes a first switch transistor, a second switch transistor, a third switch transistor, and a fourth switch transistor;
a first terminal of the first switch transistor is electrically connected to the power signal layer, a second terminal of the first switch transistor is electrically connected to the first power supply line, and a control terminal of the first switch transistor is electrically connected to a first control signal terminal;
a first terminal of the second switch transistor is electrically connected to the cathode signal layer, a second terminal of the second switch transistor is electrically connected to the second power supply line, and a control terminal of the second switch transistor is electrically connected to a second control signal terminal;
a first terminal of the third switch transistor is electrically connected to the power signal layer, a second terminal of the third switch transistor is electrically connected to the second power supply line, and a control terminal of the third switch transistor is electrically connected to a third control signal terminal; and
a first terminal of the fourth switch transistor is electrically connected to the cathode signal layer, a second terminal of the fourth switch transistor is electrically connected to the first power supply line, and a control terminal of the fourth switch transistor is electrically connected to a fourth control signal terminal.

15. The display panel according to claim 14 , wherein:
conduction types of the first switch transistor and the second switch transistor are same, and conduction types of the third switch transistor and the fourth switch transistor are same.

16. The display panel according to claim 15 , wherein:
the first control signal terminal and the second control signal terminal are a same control signal terminal, and the third control signal terminal and the fourth control signal terminal are a same control signal terminal.

17. The display panel according to claim 1 , wherein the plurality of first power voltage lines are arranged in a mesh shape.

18. The display panel according to the claim 1 , wherein:
the plurality of auxiliary electrode lines are in one-to-one correspondence with the plurality of first power voltage lines; and
an extension direction of the plurality of auxiliary electrode lines is same as an extension direction of the plurality of first power voltage lines.

19. The display panel according to claim 1 , further comprising:
an insulation layer arranged between the semiconductor layer and the power signal layer.

20. A display device, comprising a display panel, having a display region and a frame region outside the display region wherein the display region includes a plurality of pixel circuits, the display panel including:
a base substrate;
a buffer layer on a side of the base substrate, wherein the buffer layer includes an a-Si layer;
a semiconductor layer on a side of the buffer layer away from the base su

Assignees

• Wuhan Tianma Micro Electronics Co Ltd
• Wuhan Tianma Micro Electronics Co Ltd Shanghai Branch

Inventors

• Xiong Zhiyong
• Wang Yaolin
• Ding Rui

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/411 Primary

  characterised by materials, geometry or structure of the substrates · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G09F9/301

  flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title