Interface circuit, memory controller and method for calibrating signal processing devices in an interface circuit

Patent metadata

Field	Value
Publication number	US-12093131-B2
Application number	US-202318215181-A
Country	US
Kind code	B2
Filing date	Jun 28, 2023
Priority date	Jan 17, 2023
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

An interface circuit includes a signal processing circuit including multiple signal processing devices and a monitor and calibration module. The monitor and calibration module includes multiple monitor circuits, a processor and a calibration circuit. The monitor circuits monitor at least one of an amplitude, a frequency and a jitter in at least one of a reception signal and a transmission signal to correspondingly generate a monitored result and monitor at least one of power supplying voltage and ground voltage to correspondingly generate a monitored result. The processor collects the monitored results and determines a calibration operation based on the monitored results. The calibration circuit is coupled to the processor and at least one signal processing device and performs the calibration operation on the signal processing device to adjust a characteristic value of the signal processing device.

First claim

What is claimed is:

1. An interface circuit, comprising:
a signal processing circuit, configured to process a reception signal received from a host device and a transmission signal to be transmitted to the host device, wherein the signal processing circuit comprises:
a plurality of signal processing devices; and
a monitor and calibration module, comprising:
a plurality of monitor circuits, configured to monitor at least one of an amplitude, a frequency and a jitter in at least one of the reception signal and the transmission signal to generate a monitored result corresponding to the at least one of the amplitude, the frequency and the jitter in the at least one of the reception signal and the transmission signal and monitor at least one of a power supplying voltage and a ground voltage to generate a monitored result corresponding to the at least one of the power supplying voltage and the ground voltage;
a processor, configured to collect the monitored results from the monitor circuits and determine a calibration operation based on the monitored results; and
at least one calibration circuit, coupled to the processor and at least one of the signal processing devices and configured to perform the calibration operation on the at least one of the signal processing devices in response to a control signal of the processor to adjust a characteristic value of the at least one of the signal processing devices.

2. The interface circuit of claim 1 , wherein the interface circuit is configured inside of a memory controller and the signal processing circuit is a Serializer-Deserializer (SerDes).

3. The interface circuit of claim 1 , wherein the monitor circuits comprise:
a reception amplitude monitor, configured to monitor the amplitude of the reception signal, wherein the amplitude of the reception signal reflects a direct current component of the reception signal;
a reception frequency monitor, configured to monitor the frequency of the reception signal; and
a reception jitter monitor, configured to monitor the jitter in the reception signal, wherein the jitter reflects an alternating current component of the reception signal.

4. The interface circuit of claim 1 , wherein the monitor circuits comprise:
a transmission amplitude monitor, configured to monitor the amplitude of the transmission signal, wherein the amplitude of the transmission signal reflects a direct current component of the transmission signal;
a transmission frequency monitor, configured to monitor the frequency of the transmission signal; and
a transmission jitter monitor, configured to monitor the jitter in the transmission signal, wherein the jitter reflects an alternating current component of the transmission signal.

5. The interface circuit of claim 1 , wherein the monitor circuits comprise:
a power drop monitor, configured to monitor an amount of power drop in the power supplying voltage; and
a voltage bounce monitor, configured to monitor a voltage bounce in the ground voltage.

6. The interface circuit of claim 1 , wherein the signal processing devices further comprise:
a swing control circuit, configured to control a swing of the transmission signal, and wherein the at least one calibration circuit comprises:
a transmission swing calibration circuit, configured to perform the calibration operation on the swing control circuit to adjust a voltage level of an output signal of the swing control circuit.

7. The interface circuit of claim 1 , wherein the signal processing devices further comprise:
a transmission termination circuit, configured to provide a predetermined impedance on a transmission signal processing path, and wherein the at least one calibration circuit comprises:
a transmission termination calibration circuit, configured to perform the calibration operation on the transmission termination circuit to adjust an impedance value of the predetermined impedance.

8. The interface circuit of claim 1 , wherein the signal processing devices further comprise:
a frequency synthesizer circuit, configured to generate a clock signal, wherein the at least one calibration circuit comprises:
a frequency calibration circuit, configured to perform the calibration operation on the frequency synthesizer circuit to adjust a start-up voltage of a voltage controlled oscillator in the frequency synthesizer circuit.

9. The interface circuit of claim 8 , wherein the frequency synthesizer circuit comprises:
a charge pump circuit, configured to generate an output voltage as an input signal provided to the voltage controlled oscillator, and wherein the at least one calibration circuit comprises:
a charge pump calibration circuit, configured to perform the calibration operation on the charge pump circuit to adjust a level of the output voltage.

10. The interface circuit of claim 1 , wherein the signal processing devices further comprise:
a current source circuit, configured to provide a current, and wherein the at least one calibration circuit comprises:
a current source calibration circuit, configured to perform the calibration operation on the current source circuit to adjust a level of the current.

11. A memory controller, coupled to a memory device to control access operations of the memory device, comprising:
a host interface, configured to communicate with a host device and comprising a signal processing circuit to process a reception signal received from the host device and a transmission signal to be transmitted to the host device, wherein the signal processing circuit comprises:
a plurality of signal processing devices; and
a monitor and calibration module, comprising:
a plurality of monitor circuits, configured to monitor at least one of an amplitude, a frequency and a jitter in at least one of the reception signal and the transmission signal to generate a monitored result corresponding to the at least one of the amplitude, the frequency and the jitter in the at least one of the reception signal and the transmission signal and monitor at least one of a power supplying voltage and a ground voltage to generate a monitored result corresponding to the at least one of the power supplying voltage and the ground voltage;
a processor, configured to collect the monitored results from the monitor circuits and determine a calibration operation based on the monitored results; and
at least one calibration circuit, coupled to the processor and at least one of the signal processing devices and configured to perform the calibration operation on the at least one of the signal processing devices in response to a control signal of the processor to adjust a characteristic value of the at least one of the signal processing devices.

12. The memory controller of claim 11 , wherein the signal processing circuit is a Serializer-Deserializer (SerDes).

13. The memory controller of claim 11 , wherein the monitor circuits comprise:
a reception amplitude monitor, configured to monitor the amplitude of the reception signal, wherein the amplitude of the reception signal reflects a direct current component of the reception signal;
a reception frequency monitor, configured to monitor the frequency of the reception signal; and
a reception jitter monitor, configured to monitor the jitter in the reception signal, wherein the jitter reflects an alternating current component of the reception signal.

14. The memory controller of claim 11 , wherein the monitor circuits comprise:
a transmission amplitude monitor, configured to monitor the amplitude of the transmission signal, wherein the amplitude of the transmission signal reflects a direct current component of the transmission

Assignees

• Silicon Motion Inc

Inventors

• Shih Fu-Jen

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4068 Primary

  Electrical coupling · CPC title

• G06F11/3041

  where the computing system component is an input/output interface (interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units G06F13/00) · CPC title

• G06F11/3062

  where the monitored property is the power consumption (power management in a computing system G06F1/3203) · CPC title

• G06F11/3058

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title