Display substrate, display panel and display apparatus
US-2021296419-A1 · Sep 23, 2021 · US
US12089453B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12089453-B2 |
| Application number | US-202117560642-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 23, 2021 |
| Priority date | Dec 31, 2020 |
| Publication date | Sep 10, 2024 |
| Grant date | Sep 10, 2024 |
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A display apparatus includes a first pixel driving circuit, an electric field blocking layer on the first pixel driving circuit, a second pixel driving circuit on the electric field blocking layer, and a first display element and a second display element on the second pixel driving circuit, wherein each of the first pixel driving circuit and the second pixel driving circuit includes at least one thin film transistor, the first pixel driving circuit overlaps with the second pixel driving circuit, the first display element is connected with the first pixel driving circuit, and the second display element is connected with the second pixel driving circuit.
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What is claimed is: 1. A display apparatus comprising: a first pixel driving circuit; an electric field blocking layer disposed on the first pixel driving circuit; a second pixel driving circuit disposed on the electric field blocking layer; and a first display element and a second display element disposed on the second pixel driving circuit, wherein each of the first pixel driving circuit and the second pixel driving circuit includes at least one thin film transistor, the first pixel driving circuit overlaps with the second pixel driving circuit, the first display element is connected with the first pixel driving circuit, and the second display element is connected with the second pixel driving circuit. 2. The display apparatus of claim 1 , wherein the first display element overlaps with the first pixel driving circuit and the second pixel driving circuit, and wherein the second display element overlaps with the first pixel driving circuit and the second pixel driving circuit. 3. The display apparatus of claim 1 , wherein the electric field blocking layer has a thickness of 1 μm or greater between the first pixel driving circuit and the second pixel driving circuit, and wherein the thickness of the electric field blocking layer is defined as a distance between an upper surface of the first pixel driving circuit and a lower surface of the second pixel driving circuit. 4. The display apparatus of claim 1 , wherein the electric field blocking layer has a dielectric constant of 3.9 or less. 5. The display apparatus of claim 1 , wherein the electric field blocking layer includes a siloxane compound. 6. The display apparatus of claim 1 , wherein each of the first pixel driving circuit and the second pixel driving circuit includes two or more thin film transistors. 7. The display apparatus of claim 1 , wherein each of the first pixel driving circuit and the second pixel driving circuit includes four or more thin film transistors. 8. The display apparatus of claim 1 , wherein one thin film transistor of the first pixel driving circuit and one thin film transistor of the second pixel driving circuit overlap with each other, and each of the thin film transistor of the first pixel driving circuit and the thin film transistor of the second pixel driving circuit, which overlap with each other, includes: an active layer; and a gate electrode spaced apart from the active layer and at least partially overlapping with the active layer, and a spaced distance between the gate electrode of the thin film transistor of the first pixel driving circuit and the active layer of the thin film transistor of the second pixel driving circuit is 1 μm or greater. 9. The display apparatus of claim 1 , wherein the first display element includes a first electrode, a first organic light emitting layer and a second electrode, and wherein the second display element includes a first electrode, a second organic light emitting layer and a second electrode. 10. The display apparatus of claim 9 , wherein each of the first electrode of the first display element and the first electrode of the second display element has a reflective layer, and the display apparatus is a top emission type in which each of the first display element and the second display element emits light through the second electrode. 11. The display apparatus of claim 1 , further comprising: a bank layer defining a light emission area of the first display element and a light emission area of the second display element; a first connection portion for connecting the first display element with the first pixel driving circuit; and a second connection portion for connecting the second display element with the second pixel driving circuit, wherein at least one of the first connection portion and the second connection portion overlaps the bank layer. 12. The display apparatus of claim 11 , wherein at least a portion of the first connection portion overlaps with the bank layer. 13. The display apparatus of claim 11 , wherein the first connection portion includes a first portion passing through the electric field blocking layer, and wherein the first portion overlaps with the bank layer. 14. The display apparatus of claim 1 , wherein each of the thin film transistor of the first pixel driving circuit and the thin film transistor of the second pixel driving circuit includes an active layer and a gate electrode spaced apart from the active layer, and wherein a thickness ‘t’ of the electric field blocking layer satisfies the following Equation 1: t ≥( V GH /V TH )×(κ/3.9)×( t GI ), [Equation 1] where, in Equation 1, t is the thickness of the electric field blocking layer, κ is a dielectric constant of the electric field blocking layer, V GH is a turn-on voltage applied to the thin film transistor of the first pixel driving circuit, V TH is a threshold voltage of the thin film transistor of the second pixel driving circuit, and t GI is a distance between the gate electrode and the active layer of the thin film transistor of the second pixel driving circuit. 15. The display apparatus of claim 1 , wherein the second pixel driving circuit includes a buffer layer disposed on the electric field blocking layer, and the buffer layer includes an insulating material. 16. A display apparatus comprising: a first pixel including a first pixel driving circuit and a first display element connected with the first pixel driving circuit; a second pixel including a second pixel driving circuit and a second display element connected with the second pixel driving circuit; a third pixel including a third pixel driving circuit and a third display element connected with the third pixel driving circuit; a fourth pixel including a fourth pixel driving circuit and a fourth display element connected with the fourth pixel driving circuit; and an electric field blocking layer disposed between the first pixel driving circuit and the second pixel driving circuit and between the third pixel driving circuit and the fourth pixel driving circuit, wherein the first pixel driving circuit and the second pixel driving circuit overlap with each other, the third pixel driving circuit and the fourth pixel driving circuit overlap with each other, the first pixel and the second pixel constitute a first display unit, the third pixel and the fourth pixel constitute a second display unit, and the first display unit and the second display unit are adjacent to each other. 17. The display apparatus of claim 16 , wherein the electric field blocking layer has a thickness of 1 μm or greater, and wherein the thickness of the electric field blocking layer is defined as a distance between an upper surface of the first pixel driving circuit and a lower surface of the second pixel driving circuit. 18. The display apparatus of claim 16 , wherein the electric field blocking layer has a dielectric constant of 3.9 or less. 19. The display apparatus of claim 16 , wherein the electric field blocking layer includes a siloxane compound. 20. The display apparatus of claim 16 , wherein each of the first pixel driving circuit and the second pixel driving circuit includes at least one thin film transistor, each of the thin film transistor of the first pixel driving circuit and the thin film transistor of the second pixel driving circuit includes an active layer and a gate electrode spaced apart from the active layer, and wherein a thickness ‘t’ of the electric field blocking layer satisfies the following
Pixel-defining structures or layers, e.g. banks · CPC title
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