Method for manufacturing semiconductor structure

Patent metadata

Field	Value
Publication number	US-12089392-B2
Application number	US-202117457273-A
Country	US
Kind code	B2
Filing date	Dec 2, 2021
Priority date	Jan 29, 2021
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

An embodiment of the disclosure provides a method for manufacturing a semiconductor structure, including: providing a substrate, where the substrate has a peripheral region and an array region; stacking and forming an insulating layer and a mask layer with a mask pattern on the substrate; etching the insulating layer with the mask layer as a mask to form a contact hole penetrating the insulating layer at the array region; reserving the mask layer; in a direction perpendicular to a surface of the substrate, providing a thickness difference between the mask layer of the peripheral region and the mask layer of the array region; forming a first material layer; forming a second material layer; etching a part of the mask layer with the second material layer as the mask; and removing the remaining second material layer, the remaining mask layer and the first material layer on the remaining mask layer.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate, wherein the substrate has a peripheral region and an array region;
stacking and forming an insulating layer and a mask layer with a mask pattern on the substrate;
etching the insulating layer with the mask layer as a mask to form a contact hole penetrating the insulating layer at the array region; after the contact hole is formed, reserving the mask layer; and in a direction perpendicular to a surface of the substrate, providing a thickness difference between the mask layer of the peripheral region and the mask layer of the array region;
forming a first material layer, wherein a surface of the mask layer and a surface of the contact hole of the array region are at least covered with the first material layer;
forming a second material layer, wherein the second material layer is located on the first material layer;
etching a part of the mask layer with the second material layer as the mask to reduce the thickness difference between the mask layer of the peripheral region and the mask layer of the array region; and
removing the remaining second material layer, the remaining mask layer, and the remaining first material layer on the mask layer.

2. The method for manufacturing the semiconductor structure according to claim 1 , wherein the surface of the mask layer of the peripheral region is also covered with the first material layer; a process step for etching a part of the mask layer with the second material layer as the mask further comprises: etching the first material layer on the mask layer located at the peripheral region.

3. The method for manufacturing the semiconductor structure according to claim 2 , wherein a process step for forming the second material layer comprises:
forming an initial second material layer, wherein a surface of the first material layer is covered with the initial second material layer, and a top surface of the initial second material layer is higher than the highest surface of the first material layer; and
removing a part of the initial second material layer to expose the highest surface of the first material layer to form the second material layer.

4. The method for manufacturing the semiconductor structure according to claim 2 , wherein the first material layer of the array region is only covered with the second material layer.

5. The method for manufacturing the semiconductor structure according to claim 3 , wherein the second material layer is a flowable medium.

6. The method for manufacturing the semiconductor structure according to claim 4 , wherein the second material layer is a flowable medium.

7. The method of manufacturing the semiconductor structure according to claim 5 , wherein the flowable medium comprises a photoresist or a dielectric medium containing a Si—H bond, a Si—N bond, and an N—H bond.

8. The method of manufacturing the semiconductor structure according to claim 7 , wherein the method for forming the second material layer comprises a chemical vapor deposition process or a spin coating process.

9. The method of manufacturing the semiconductor structure according to claim 1 , wherein the material of the mask layer comprises polysilicon.

10. The method of manufacturing the semiconductor structure according to claim 1 , wherein the first material layer is made of a capacitor electrode material.

11. The method of manufacturing the semiconductor structure according to claim 1 , wherein process steps for removing the remaining second material layer, the remaining mask layer, and the remaining first material layer on the mask layer comprises:
etching a part of the remaining second material layer to expose the first material layer on the remaining mask layer; and
removing the remaining mask layer and the first material layer on the remaining mask layer with the remaining second material layer as the mask; and removing the remaining second material layer.

12. The method for manufacturing the semiconductor structure according to claim 1 , wherein a method for removing a part of the second material layer to expose a highest surface of the first material layer comprises etching or chemical mechanical polishing.

13. The method of manufacturing the semiconductor structure according to claim 1 , wherein process steps for forming the insulating layer comprises: forming a dielectric layer on the substrate, and forming a supporting layer on the dielectric layer.

14. The method for manufacturing the semiconductor structure according to claim 13 , wherein a process step for forming the dielectric layer comprises: sequentially stacking and forming a first stabilizing layer, a first isolating layer, a second stabilizing layer, and a second isolating layer on the substrate.

Assignees

• Changxin Memory Tech Inc

Inventors

• Xia Jun
• Wan Qiang
• Xu Penghui
• Liu Tao
• Li Sen
• Zhan Kangshu

Classifications

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title

• H10B12/30

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• G11C5/10

  for interconnecting capacitors · CPC title

• H10B12/033

  the capacitor extending over the transistor · CPC title