Excess loop delay compensation for a delta-sigma modulator

Patent metadata

Field	Value
Publication number	US-12088324-B2
Application number	US-202217820975-A
Country	US
Kind code	B2
Filing date	Aug 19, 2022
Priority date	Aug 19, 2022
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

In accordance with an embodiment, a delta-sigma modulator includes: an analog loop filter comprising an outer portion and an inner portion having an input coupled to the outer portion; a quantizer coupled to an output of the inner portion of the analog loop filter; an outer feedback path coupled between an output of the quantizer and an input to the outer portion of the analog loop filter; and a compensation filter coupled between an output of the quantizer and an input of the inner portion of the analog loop filter. The compensation filter has a transfer function configured to correct for an effect of excess loop delay (ELD) on the delta-sigma modulator.

First claim

What is claimed is:

1. A delta-sigma modulator comprising:
an analog loop filter comprising an outer portion and an inner portion having an input coupled to the outer portion;
a quantizer coupled to an output of the inner portion of the analog loop filter;
an outer feedback path coupled between an output of the quantizer and an input of the outer portion of the analog loop filter; and
a compensation filter coupled between an output of the quantizer and an input of the inner portion of the analog loop filter, wherein:
the compensation filter has a transfer function configured to correct for an effect of an outer excess loop delay (ELD) and an inner ELD on the delta-sigma modulator,
the outer ELD comprises a delay from the input of the quantizer to the input of the outer portion of the analog loop filter including the outer feedback path, and the inner ELD comprises a delay from the input to the quantizer to the input of the inner portion of the analog loop filter including at least a portion of the outer feedback path,
the inner ELD is less than one clock cycle of the delta-sigma modulator, and
the outer ELD is at least two clock cycles of the delta-sigma modulator.

2. The delta-sigma modulator of claim 1 , wherein:
the input of the inner portion of the analog loop filter comprises one or more inputs;
the delta-sigma modulator comprises one or more inner feedback paths coupled between the output of the quantizer and respective ones of the one or more inputs of the inner portion of the analog loop filter; and
the compensation filter is disposed within one of the one or more inner feedback paths.

3. The delta-sigma modulator of claim 2 , wherein the one or more inner feedback paths comprises an innermost feedback path coupled to a last input of the inner portion of the analog loop filter, wherein a portion of the inner portion of the analog loop filter disposed between the last input of the inner portion of the analog loop filter and the output of the inner portion of the analog loop filter has an order of zero.

4. The delta-sigma modulator of claim 2 , wherein:
the one or more inner feedback paths comprises a first digital-to-analog converter (DAC);
the outer feedback path comprises a functional circuit coupled to a second DAC; and
the compensation filter comprises a finite impulse response (FIR) filter.

5. The delta-sigma modulator of claim 1 , further comprising a functional circuit disposed within the outer feedback path.

6. The delta-sigma modulator of claim 5 , wherein the functional circuit has a finite processing time and comprises at least one of:
a dynamic element matching (DEM) circuit;
an inter-symbol interference (ISI) correction circuit; or
a jitter reduction filter.

7. The delta-sigma modulator of claim 1 , wherein the transfer function of the compensation filter is configured to correct for an effect of the outer ELD and the inner ELD on a noise transfer function of the delta-sigma modulator.

8. The delta-sigma modulator of claim 1 , wherein the analog loop filter comprises a cascade of integrators or resonators, wherein the cascade of resonators or integrators comprises distributed feedback paths, feed-forward paths, or a combination of distributed feedback paths and feed-forward paths.

9. A circuit comprising:
a delta-sigma modulator comprising:
an analog loop filter of order n comprising:
a first analog loop filter portion having an order n1 of between 1 and p, wherein p is an integer of at least one and of at most n, and
a second analog loop filter portion having an input coupled to an output of the first analog loop filter portion, the second analog loop filter portion having an order of p-n,

a quantizer coupled to an output of the second analog loop filter portion, the quantizer having a first excess loop delay (ELD) and configured to provide a quantized sample every sampling period,
an inner loop portion coupled between an output of the quantizer and an input of the second analog loop filter portion, the inner loop portion having a second ELD, the inner loop portion comprising a finite impulse response (FIR) filter and a first digital-to-analog converter (DAC) coupled between an output of the FIR filter and the input of the second analog loop filter portion,
a functional circuit coupled between the output of the quantizer and an input of the first analog loop filter portion, and
a second DAC having an input coupled to the output of the functional circuit and an output coupled to an input of the first analog loop filter portion, wherein the second DAC and the functional circuit have a third ELD, a sum of the first ELD and the second ELD is not larger than one clock cycle of the delta-sigma modulator, and the third ELD is larger than one clock cycle of the delta-sigma modulator, and wherein the FIR filter is configured to correct for an effect of the first ELD, the second ELD, and the third ELD on a noise transfer function of the delta-sigma modulator.

10. The circuit of claim 9 , wherein a sum of the first ELD, the second ELD and the third ELD is greater than two sampling periods.

11. The circuit of claim 9 , wherein the functional circuit comprises:
a dynamic element matching circuit;
a digital delta-sigma modulator;
an intersymbol interference correction circuit; or
a jitter reduction filter.

12. The circuit of claim 9 , further comprising a decimation filter coupled to an output of the quantizer.

13. The circuit of claim 9 , wherein:
the input of the second analog loop filter portion of the analog loop filter comprises a plurality of inputs; and
the inner loop portion comprises a plurality of feedback loops coupled between the output of the quantizer and respective inputs of the plurality of inputs of the second analog loop filter portion.

14. The circuit of claim 9 , wherein:
the first analog loop filter portion comprises a first set of one or more integrators or resonators, wherein the first set comprises distributed feedback paths, feed-forward paths, or a combination of distributed feedback paths and feed-forward paths; and
the second analog loop filter portion comprises a second set of one or more integrators or resonators, wherein the second set comprises distributed feedback paths, feed-forward paths, or a combination of distributed feedback paths and feed-forward paths.

15. The circuit of claim 9 , wherein the analog loop filter comprises a continuous-time filter.

16. A method of operating a delta-sigma modulator, the method comprising:
filtering an analog input signal using an analog loop filter, wherein the analog loop filter comprises an outer portion, and an inner portion coupled to an output of the inner portion;
quantizing an output of the inner portion of the analog loop filter to form a quantized signal using a quantizer;
feeding back the quantized signal to an input of the outer portion of the analog loop filter via an outer feedback path;
filtering the quantized signal to form a filtered signal using a compensation filter; and
feeding back the filtered signal to an input of the inner portion of the analog loop filter, wherein:
the compensation filter has a transfer function configured to correct for an effect of an outer excess loop delay (ELD) and an inner ELD on the delta-sigma modulator,
the outer ELD comprises a delay from the input of the quantizer to the input of the outer portion of the analog loop filter including the outer feedback path, and the inner ELD comprises a delay from the input to the quantizer to the input of the inner portion of the analog loop filter including at least a portion

Assignees

• Infineon Technologies Ag

Inventors

• Abdelaal Ahmed
• Kauffman John G
• Ortmanns Maurits
• Miki Takashi

Classifications

• H03M3/422

  having one quantiser only · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/436

  characterised by the order of the loop filter, e.g. error feedback type · CPC title

• H03M3/372 Primary

  Jitter reduction · CPC title

• H03M3/43

  the quantiser being a single bit one · CPC title