Semiconductor devices and methods of manufacturing semiconductor devices

Patent metadata

Field	Value
Publication number	US-12087760-B2
Application number	US-202217662263-A
Country	US
Kind code	B2
Filing date	May 6, 2022
Priority date	May 6, 2022
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

In an example, a semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor region of the first conductivity type over the semiconductor substrate. A well region of a second conductivity type is in the semiconductor region. A doped region of the first conductivity type is in the well region. A doped region of the second conductivity type is in the well region. A doped region of the second conductivity type is in the semiconductor substrate at a bottom side. A doped region of the first conductivity type is in the semiconductor substrate at the bottom side. A first conductor is at a top side of the semiconductor region and a second conductor is at the bottom side. In some examples, one or more of doped regions at the bottom side is a patterned doped region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a region of semiconductor material comprising:
a top side;
a bottom side opposite to the top side;
a semiconductor substrate of a first conductivity type; and
a semiconductor region of the first conductivity type over the semiconductor substrate;

a well region of a second conductivity type opposite to the first conductivity type in the semiconductor region;
a first doped region of the first conductivity type in the well region;
a second doped region of the second conductivity type in the well region;
a third doped region of the second conductivity type in the semiconductor substrate at the bottom side;
a fourth doped region of the first conductivity type in the semiconductor substrate at the bottom side;
a first conductor coupled to the first doped region and the second doped region at the top side; and
a second conductor coupled to the third doped region and the fourth doped region at the bottom side;
wherein:
one or more of the third doped region or the fourth doped region is a patterned doped region; and
the semiconductor device is configured as a dual-sided semiconductor-controlled rectifier (SCR) device.

2. The semiconductor device of claim 1 , wherein:
both the third doped region and the fourth doped region are patterned doped regions;
the third doped region has a first width in a cross-sectional view;
the fourth doped region comprises two portions each on opposing sides of the third doped region in the cross-sectional view;
the two portions of the fourth doped region sum to a second width in the cross-sectional view; and
the first width is different than the second width.

3. The semiconductor device of claim 2 , wherein:
the first width is less than the second width.

4. The semiconductor device of claim 2 , wherein:
the first width is greater than the second width.

5. The semiconductor device of claim 1 , wherein:
the semiconductor substrate has a thickness between 75 microns and 140 microns.

6. The semiconductor device of claim 1 , wherein:
the semiconductor substrate has a dopant concentration between 1.0×10 16 atoms/cm 3 and 4.0×10 16 atoms/cm 3 .

7. The semiconductor device of claim 1 , wherein:
the second doped region comprises two portions on opposing sides of the first doped region in a cross-sectional view.

8. The semiconductor device of claim 1 , further comprising:
a substrate having a die pad and leads, wherein the second conductor of the semiconductor device is attached to the die pad with a first attachment material, and the first conductor is coupled to the leads with an interconnect; and
a package body encapsulating the semiconductor device and at least portions of the interconnect.

9. The semiconductor device of claim 8 , wherein:
the die pad is a metal;
the first attachment material comprises a high thermal conductivity material; and
the second conductor has a thickness between 2 microns and 9 microns.

10. The semiconductor device of claim 1 , wherein:
the third doped region and the fourth doped region are ion implanted regions.

11. A semiconductor device, comprising:
a region of semiconductor material comprising:
a top side;
a bottom side opposite to the top side;
a semiconductor substrate of a first conductivity type and a semiconductor substrate thickness; and
a semiconductor region of the first conductivity type over the semiconductor substrate, wherein the semiconductor region has a higher peak dopant concentration than the semiconductor substrate;

a well region of a second conductivity type opposite to the first conductivity type in the semiconductor region;
a first doped region of the first conductivity type in the well region;
a second doped region of the second conductivity type in the well region laterally adjacent to the first doped region;
a third doped region of the second conductivity type in the semiconductor substrate at the bottom side;
a fourth doped region of the first conductivity type in the semiconductor substrate at the bottom side laterally adjacent to the third doped region;
an anode terminal coupled to the first doped region and the second doped region at the top side; and
a cathode terminal coupled to the third doped region and the fourth doped region at the bottom side;
wherein:
the fourth doped region is a patterned doped region; and
the fourth doped region comprises two portions that are on opposing sides of the third doped region in a cross-sectional view.

12. The semiconductor device of claim 11 , wherein:
the third doped region is a patterned doped region;
the semiconductor substrate thickness is between 70 microns and 100 microns; and
the semiconductor device is configured as a two-terminal dual-sided vertical semiconductor-controlled rectifier (SCR) device.

13. The semiconductor device of claim 11 , wherein:
the cathode terminal is thicker than the anode terminal.

14. The semiconductor device of claim 12 , wherein:
the semiconductor device has a device width in the cross-sectional view;
the third doped region has a first width in the cross-sectional view;
the two portions of the fourth doped region sum to a second width in the cross-sectional view; and
the first width is between 40% and 60% of the device width.

15. The semiconductor device of claim 14 , wherein:
the semiconductor device is configured as a two-terminal dual-sided vertical semiconductor-controlled rectifier (SCR) device;
the second width is different that the first width; and
the second width is pre-selected to adjust holding current of the SCR device to a predetermined level.

16. A method of manufacturing a semiconductor device, comprising:
providing a region of semiconductor material comprising:
a top side;
a semiconductor substrate of a first conductivity type; and
a semiconductor region of the first conductivity type over the semiconductor substrate;

providing a well region of a second conductivity type opposite to the first conductivity type in the semiconductor region;
providing a first doped region of the first conductivity type in the well region;
providing a second doped region of the second conductivity type in the well region;
providing a first conductor coupled to the first doped region and the second doped region at the top side;
reducing thickness of the semiconductor substrate to provide the semiconductor substrate with a substrate thickness and to define a bottom side of the region of semiconductor material opposite to the top side;
forming a third doped region of the second conductivity type in the semiconductor substrate at the bottom side;
selectively forming a fourth doped region of the first conductivity type in the semiconductor substrate at the bottom side; and
providing a second conductor coupled to the third doped region and the fourth doped region at the bottom side;
wherein:
the semiconductor device is configured as a two-terminal dual-sided semiconductor-controlled rectifier (SCR) device.

17. The method of claim 16 , wherein:
reducing the thickness of the semiconductor substrate comprises providing the substrate thickness between 75 microns and 140 microns.

18. The method of claim 16 , wherein:
providing the region of semiconductor material includes providing the region of semiconductor material as part of a semiconductor wafer; and
reducing the thickness comprises reducing the thickness of the semiconductor wafer at a center portion of the semiconductor wafer while leaving an outer ring of material at a peri

Assignees

• Semiconductor Components Ind Llc

Inventors

• Johnson Derrick
• Chen Yupeng
• Wall Ralph N
• Griswold Mark

Classifications

• H10D84/859

  comprising both N-type and P-type wells, e.g. twin-tub · CPC title

• H10D18/00

  Thyristors · CPC title

• H10D62/206

  Cathode base regions of thyristors · CPC title

• H10D62/199

  Anode base regions of thyristors · CPC title

• H10D89/713 Primary

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title