Bias voltage generation circuit for memory devices

Patent metadata

Field	Value
Publication number	US-12087384-B2
Application number	US-202217668962-A
Country	US
Kind code	B2
Filing date	Feb 10, 2022
Priority date	Feb 10, 2022
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

The present disclosure relates to memory devices and, more particularly, to bias voltage generation circuit for memory devices and methods of operation. The voltage generation circuit includes: an internal voltage generator which providing a bias voltage to at least one internal node of a bias voltage generation circuitry; and at least one pre-charging circuitry providing a predefined bias voltage to at least one internal node including a distributed network of local drivers.

First claim

What is claimed:

1. An apparatus, comprising:
an internal voltage generator providing a bias voltage to at least one internal node of a bias voltage generation circuitry;
at least one pre-charging circuitry providing a predefined bias voltage to the at least one internal node including a distributed network of local drivers; and
an error amplifier downstream from the internal voltage generator and the at least one pre-charging circuitry, the error amplifier comparing a final voltage to the predefined bias voltage,
wherein the at least one pre-charging circuitry comprises a plurality of precharge circuits which turn on for a predefined period of time during wake-up of a non-volatile memory.

2. The apparatus of claim 1 , wherein the at least one internal node comprises one or more local drivers.

3. The apparatus of claim 1 , wherein the pre-charging circuitry is distributed across a chip.

4. The apparatus of claim 1 , wherein the predefined bias voltage accelerates a wake-up time of a read operation in non-volatile memory.

5. The apparatus of claim 1 , wherein the predefined bias voltage comprises a value close to a final voltage value of the internal voltage generator.

6. The apparatus of claim 1 , wherein the at least one pre-charging circuitry comprises driving FETs sized to reduce a time of charging/discharging load capacitance.

7. The apparatus of claim 6 , wherein driving FETs which are turned off after bias stabilization to save power.

8. The apparatus of claim 1 , wherein the at least one pre-charging circuitry comprises a chain of resistors.

9. The apparatus of claim 1 , wherein the at least one pre-charging circuitry comprises transistors which are shorted together and are in series with a resistor.

10. The apparatus of claim 1 , further comprising a short-pulse generator which provides a pulse to the least one pre-charging circuitry.

11. A voltage bias generator comprising:
a first predefined voltage generator which generates an internal voltage bias to at least one internal node;
a first internal voltage generator which generates a final internal voltage bias to the at least one internal node;
a distributed final local driver which receives the final internal voltage bias and provides a local final bias to circuit blocks for non-volatile memory operation; and
an error amplifier downstream from the first internal voltage generator and a pre-charging circuitry, the error amplifier comparing a final voltage to a predefined bias voltage of the pre-charging circuitry,
wherein the distributed final local driver includes a second predefined voltage generator and a second internal voltage generator in series with a local bias driver.

12. The voltage bias generator of claim 11 , further comprising a short pulse generator that provides a wake-up pulse to the first predefined voltage generator and the second predefined voltage generator.

13. The voltage bias generator of claim 11 , wherein the first predefined voltage generator comprises a series of transistors which provide the internal voltage bias to the error amplifier.

14. The voltage bias generator of claim 11 , wherein the first predefined voltage generator comprises a resistor chain.

15. The voltage bias generator of claim 11 , wherein the first predefined voltage generator comprises transistors which are shorted together and are in series with a resistor.

16. A method, comprising:
providing a predefined bias voltage to at least one internal node of a bias voltage generation circuitry; and
providing a final bias voltage to at least one internal node; and
providing a final bias voltage by using distributed local drivers of the bias voltage generation circuitry,
wherein the at least one internal node includes an error amplifier which compares the precharge bias voltage to the final bias voltage and sends the final bias voltage to a distributed network of local drivers,
wherein the final bias voltage to at least one internal node is provided by driving FETs which are turned off after bias stabilization to save power.

Assignees

• Globalfoundries Us Inc

Inventors

• Yin Ming
• Paul Bipul C
• Gaul Nishtha
• Nemawarkar Shashank

Classifications

• G11C5/148

  Details of power up or power down circuits, standby circuits or recovery circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title