Method for programming an array of resistive memory cells

Patent metadata

Field	Value
Publication number	US-12087360-B2
Application number	US-202217831948-A
Country	US
Kind code	B2
Filing date	Jun 3, 2022
Priority date	Jun 4, 2021
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

A method for programming at least one resistive memory cell of an array of resistive memory cells, includes a sequence of N programming cycles, N being an integer greater than or equal to 2, each programming cycle including a set procedure and a reset procedure, each set procedure including the application of a set technique chosen among a plurality of set techniques, the method including acquiring a bit error ratio value corresponding to each programming cycle for each set technique; and at each programming cycle, applying the set technique having the lowest bit error ratio value corresponding to the programming cycle.

First claim

The invention claimed is:

1. A method for programming at least one resistive memory cell of an array of resistive memory cells, said method comprising a sequence of N programming cycles, N being an integer greater than or equal to 2, each programming cycle comprising a set step and a reset step, each set step comprising application of a set technique chosen among a plurality of set techniques, wherein each resistive memory cell comprises a resistive memory element and a selection transistor connected in series with the resistive memory element and wherein the plurality of set techniques comprises:
full reprogramming: said full reprogramming comprising applying at least on reprogramming cycles, each reprogramming cycle comprising a reset operation followed by a set operation followed by a read and verify operation; and
verify Set V TE : said verify Set V TE comprises applying voltage pulses with increasing positive amplitudes on a top electrode of the resistive memory element; and
verify Set V G : said verify Set V G comprises applying voltage pulses with increasing positive amplitudes on a gate of the selection transistor;

said method comprising the following steps:
acquiring a bit error ratio value corresponding to each programming cycle for each set technique of said plurality of set techniques;
at each programming cycle, applying the set technique having a lowest bit error ratio value corresponding to said programming cycle.

2. The method according to claim 1 , wherein the plurality of set techniques are algorithms comprising set operation, and reset operations, and read and verify operations.

3. The method according to claim 1 , wherein the bit error ratio value corresponding to each programming cycle for each set technique is measured prior to the programming cycles by characterizing a reference array of resistive memory cells and a sequence of the set techniques to be applied during the programming cycles is then defined.

4. The method according to claim 1 , wherein the bit error ratio value corresponding to each programming cycle for each set technique is acquired from a database.

5. The method according to claim 4 , wherein the bit error ratio value corresponding to each programming cycle for each set technique is measured prior to the programming cycles by characterizing a reference array of resistive memory cells and then stored in the database.

6. An electronic circuit comprising an array of resistive memory cells and a system for implementing the programming method according to claim 1 , wherein each resistive memory cell comprises a resistive memory element and a selection transistor connected in series with the resistive memory element, said system comprising:
a power source configured to generate voltage pulses;
an addressing circuit configured to apply the voltage pulses:
to the top electrode of at least a memory resistive element of the array of resistive memory cells; and
to the gate of the selection transistor; and

a controller configured to send control signals to the power source so that it generates the voltage pulses corresponding to the set techniques having the lowest bit error rate.

7. A method for programming at least one resistive memory cell of an array of resistive memory cells, said method comprising a sequence of N programming cycles, N being an integer greater than or equal to 2, each programming cycle comprising a set step and a reset step, each set step comprising application of a set technique chosen among a plurality of set techniques, wherein each resistive memory cell comprises a resistive memory element and a selection transistor connected in series with the resistive memory element and wherein the plurality of set techniques comprises:
full reprogramming: said full reprogramming comprising applying at least on reprogramming cycles, each reprogramming cycle comprising a reset operation followed by a set operation followed by a read and verify operation; and
verify Set V TE : said verify Set V TE comprises applying voltage pulses with increasing positive amplitudes on a top electrode of the resistive memory element; and
verify Set V G : said verify Set V G comprises applying voltage pulses with increasing positive amplitudes on a gate of the selection transistor;

said method comprising the following steps:
acquiring a bit error ratio value corresponding to each programming cycle for each set technique of said plurality of set techniques;
at each programming cycle, applying the set technique having a lowest bit error ratio value corresponding to said programming cycle,
wherein the bit error ratio value corresponding to each programming cycle for each set technique is measured prior to the programming cycles by characterizing a reference array of resistive memory cells and a sequence of the set techniques to be applied during the programming cycles is then defined.

8. A method for programming at least one resistive memory cell of an array of resistive memory cells, said method comprising a sequence of N programming cycles, N being an integer greater than or equal to 2, each programming cycle comprising a set step and a reset step, each set step comprising application of a set technique chosen among a plurality of set techniques, wherein each resistive memory cell comprises a resistive memory element and a selection transistor connected in series with the resistive memory element and wherein the plurality of set techniques comprises:
full reprogramming: said full reprogramming comprising applying at least on reprogramming cycles, each reprogramming cycle comprising a reset operation followed by a set operation followed by a read and verify operation; and
verify Set V TE : said verify Set V TE comprises applying voltage pulses with increasing positive amplitudes on a top electrode of the resistive memory element; and
verify Set V G : said verify Set V G comprises applying voltage pulses with increasing positive amplitudes on a gate of the selection transistor;

said method comprising the following steps:
acquiring a bit error ratio value corresponding to each programming cycle for each set technique of said plurality of set techniques;
at each programming cycle, applying the set technique having a lowest bit error ratio value corresponding to said programming cycle,
wherein the bit error ratio value corresponding to each programming cycle for each set technique is acquired from a database, and
wherein the bit error ratio value corresponding to each programming cycle for each set technique is measured prior to the programming cycles by characterizing a reference array of resistive memory cells and then stored in the database.

Assignees

• Commissariat Energie Atomique
• Weebit Nano Ltd

Inventors

• Molas Gabriel
• Bricalli Alessandro
• Piccolboni Guiseppe
• Regev Amir

Classifications

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C13/0064

  Verifying circuits or methods · CPC title

• G11C2013/0092

  Write characterized by the shape, e.g. form, length, amplitude of the write pulse · CPC title

• G11C13/0035

  Evaluating degradation, retention or wearout, e.g. by counting writing cycles · CPC title

• G11C2013/0073

  Write using bi-directional cell biasing · CPC title