Chips including classical and quantum computing processors

Patent metadata

Field	Value
Publication number	US-12086091-B2
Application number	US-202217575552-A
Country	US
Kind code	B2
Filing date	Jan 13, 2022
Priority date	Mar 21, 2014
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

An apparatus includes a substrate, a classical computing processor formed on the substrate, a quantum computing processor formed on the substrate, and one or more coupling components between the classical computing processor and the quantum computing processor, the one or more coupling components being formed on the substrate and being configured to allow data exchange between the classical computing processor and the quantum computing processor.

First claim

What is claimed is:

1. A method of operating a quantum computing system, the method comprising:
using a refrigeration system to cool a chip comprising a classical computing processor and a quantum computing processor, to cause a material of the classical computing processor and the quantum computing processor to become superconducting;
performing a quantum computation on the quantum computing processor, to obtain a quantum computation result;
obtaining the quantum computation result at the classical computing processor through a direct coupling between a superconducting flux qubit of the quantum computing processor and a superconducting flux bit of the classical computing processor; and
obtaining an output at a data storage device through a coupling between the classical computing processor and the data storage device, wherein the output is based on the quantum computation result, and
wherein the chip is within the refrigeration system, and wherein the data storage device is external to the refrigeration system.

2. The method of claim 1 , wherein the quantum computation is based on a quantum annealing algorithm, and
wherein the output is based on a classical probabilistic algorithm.

3. The method of claim 2 , comprising:
performing a classical computation on the classical computing processor, to obtain a classical computation result; and
obtaining the classical computation result at the quantum computing processor,
wherein the classical computation result is used as a seed for the quantum annealing algorithm used in the quantum computation.

4. The method of claim 1 , wherein the quantum computation result comprises a quantum state, and wherein the method comprises:
projecting the quantum state to a classical computational basis; and
using the classical computing processor, performing a classical computation using the quantum state projected to the classical computational basis as an ansatz.

5. The method of claim 1 , wherein the direct coupling comprises a plurality of inductive couplers formed on the chip.

6. The method of claim 1 , wherein the direct coupling comprises a mutual inductive coupling between the superconducting flux qubit and the superconducting flux bit.

7. The method of claim 1 , wherein the output is based on an overall quantum and classical Markov chain process that includes the quantum computation and at least one classical computation.

8. The method of claim 1 , wherein performing the quantum computation comprises applying a driving magnetic field to the chip,
wherein a strength of the driving magnetic field does not cause a first order or second order phase transition in the quantum computing processor.

9. The method of claim 1 , wherein the classical computing processor comprises a plurality of reciprocal quantum logic gates.

10. The method of claim 1 , wherein the quantum computation result comprises parameters of a neural network model.

11. An apparatus comprising:
a chip comprising a classical computing processor, a quantum computing processor, and a direct coupler between a superconducting flux bit of the classical computing processor and a superconducting flux qubit of the quantum computing processor;
a refrigeration system enclosing the chip; and
a data storage device communicatively coupled to the classical computing processor, the data storage device external to the refrigeration system,
wherein the classical computing processor and the quantum computing process are configured to perform operations comprising:
performing a quantum computation on the quantum computing processor, to obtain a quantum computation result;
obtaining the quantum computation result at the classical computing processor through the direct coupler; and
obtaining an output at the data storage device, wherein the output is based on the quantum computation result.

12. The apparatus of claim 11 , wherein the quantum computation is based on a quantum annealing algorithm, and
wherein the output is based on a classical probabilistic algorithm.

13. The apparatus of claim 12 , wherein the operations comprise:
performing a classical computation on the classical computing processor, to obtain a classical computation result; and
obtaining the classical computation result at the quantum computing processor,
wherein the classical computation result is used as a seed for the quantum annealing algorithm used in the quantum computation.

14. The apparatus of claim 11 , wherein the quantum computation result comprises a quantum state, and wherein the operations comprise:
projecting the quantum state to a classical computational basis; and
using the classical computing processor, performing a classical computation using the quantum state projected to the classical computational basis as an ansatz.

15. The apparatus of claim 11 , wherein the direct coupler comprises a plurality of inductive couplers formed on the chip.

16. The apparatus of claim 11 , wherein the direct coupler comprises a mutual inductive coupler between the superconducting flux bit and the superconducting flux qubit.

17. The apparatus of claim 11 , wherein the output is based on an overall quantum and classical Markov chain process that includes the quantum computation and at least one classical computation.

18. The apparatus of claim 11 , wherein performing the quantum computation comprises applying a driving magnetic field to the chip,
wherein a strength of the driving magnetic field does not cause a first order or second order phase transition in the quantum computing processor.

19. The apparatus of claim 11 , wherein the classical computing processor comprises a plurality of reciprocal quantum logic gates.

20. The apparatus of claim 11 , wherein the quantum computation result comprises parameters of a neural network model.

21. The method of claim 6 , comprising adjusting the direct coupling between the classical computing processor and the quantum computing processor by controlling a current in an inductive coupler providing the mutual inductive coupling, wherein the inductive coupler is included in the chip.

22. The apparatus of claim 16 , wherein the mutual inductive coupler is configured such that a current in the mutual inductive coupler controls a coupling between the classical computing processor and the quantum computing processor.

Assignees

• Google Llc

Inventors

• Mohseni Masoud
• Neven Hartmut

Classifications

• G06N10/60

  Quantum algorithms, e.g. based on quantum optimisation, quantum Fourier or Hadamard transforms · CPC title

• G06N10/40

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title

• G06N10/20

  Models of quantum computing, e.g. quantum circuits or universal quantum computers · CPC title

• H01P5/08

  for linking dissimilar lines or devices (H01P1/16, H01P5/04 take precedence; linking lines of the same kind but with different dimensions H01P5/02) · CPC title

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title