Display panel, display device, and driving method therefor

Patent metadata

Field	Value
Publication number	US-12085822-B2
Application number	US-202117764548-A
Country	US
Kind code	B2
Filing date	Jun 9, 2021
Priority date	Jul 29, 2020
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

A display panel, a display device, and a driving method therefor, the display panel comprising: a plurality of sub-pixels arranged in an array, and the display panel comprising: a first substrate and a second substrate disposed opposite each other, wherein the first substrate comprises a first base and a plurality of pixel electrodes disposed on the first base, and each sub-pixel comprises at least two pixel electrodes.

First claim

The invention claimed is:

1. A display panel, comprising a plurality of sub-pixels arranged in an array, the display panel comprising a first substrate and a second substrate which are arranged opposite to each other; the first substrate comprising a first base substrate and a plurality of pixel electrodes arranged on the first base substrate; and
each sub-pixel comprising at least two pixel electrodes,
wherein a plurality of sub-pixels constitute one pixel;
the second substrate comprises a second base substrate and a color filter layer arranged on the second base substrate, the color filter layer comprising a plurality of optical filters arranged in a matrix;
each sub-pixel further comprises an optical filter of a planar structure; and optical filters of a plurality of sub-pixels located in a same pixel have different colors; and
in each sub-pixel, an orthographic projection of the optical filter on the first base substrate overlaps at least partially with an orthographic projection of each pixel electrode on the first base substrate.

2. The display panel according to claim 1 , wherein the first substrate further comprises an array structure layer arranged on one side of the pixel electrodes close to the first base substrate;
the array structure layer comprises a plurality of transistors in a one-to-one correspondence with the pixel electrodes, the pixel electrodes being electrically connected to the corresponding transistors; and
each sub-pixel further comprises transistors corresponding to the at least two pixel electrodes.

3. The display panel according to claim 2 , wherein the second substrate further comprises a black matrix layer, a first adhesive layer and a common electrode, which are arranged on the second base substrate and are arranged in the same layer as the color filter layer, the black matrix layer comprising a plurality of black matrix structures;
each sub-pixel further comprises a black matrix structure provided with an opening area, the optical filter being located in the opening area and the black matrix structures of adjacent sub-pixels being connected to each other;
in each sub-pixel, an orthographic projection of the black matrix structure on the first base substrate covers orthographic projections of all the transistors on the first base substrate, and the orthographic projection of the black matrix structure on the first base substrate overlaps at least partially with the orthographic projection of each pixel electrode on the first base substrate; and
the first adhesive layer is arranged on one side of the color filter layer close to the first substrate, and the common electrode is arranged on one side of the first adhesive layer close to the first substrate.

4. The display panel according to claim 3 , wherein the first substrate further comprises a plurality of data signal lines extending along a first direction and a plurality of scan signal lines extending along a second direction, which are arranged on the first base substrate; and
an orthographic projection of the black matrix layer on the first base substrate covers orthographic projections of the data signal lines and the scan signal lines on the first base substrate, the first direction being perpendicular to the second direction.

5. The display panel according to claim 4 , wherein the at least two pixel electrodes in each sub-pixel are arranged along the first direction;
each pixel electrode is in a shape of a broken line, and comprises a first connecting portion and a second connecting portion, the first connecting portion and the second connecting portion being both linear and being an integrally formed structure, the second connecting portion extending along the second direction;
the first connecting portion is connected to the transistor corresponding to the pixel electrode, and the orthographic projection of the black matrix structure on the first base substrate covers an orthographic projection of the first connecting portion on the first base substrate;
an orthographic projection of the second connecting portion on the first base substrate overlaps at least partially with the orthographic projection of the optical filter on the first base substrate, and the orthographic projection of the second connecting portion on the first base substrate overlaps at least partially with the orthographic projection of the black matrix structure on the first base substrate; and
a width of the second connecting portion of each pixel electrode along the first direction is 1.3 microns to 1.7 microns.

6. The display panel according to claim 5 , wherein each sub-pixel is electrically connected to two scan signal lines and M data signal lines respectively, the two scan signal lines are a first scan signal line and a second scan signal line respectively, the M data signal lines are a first data signal line to an Mth data signal line respectively, the at least two pixel electrodes arranged along the first direction in each sub-pixel are a first pixel electrode to a 2Mth pixel electrode sequentially, and a transistor corresponding to an ith pixel electrode is an ith transistor; the optical filter in each sub-pixel is an axisymmetric structure, and symmetry axes of the optical filter comprise a first symmetry axis and a second symmetry axis, the first symmetry axis extending along the first direction and the second symmetry axis extending along the second direction;
a first transistor to an Mth transistor are arranged along the second direction, an M+1th transistor to a 2Mth transistor are arranged along the second direction, a jth transistor and a j+Mth transistor are arranged along the first direction, and the jth transistor and the j+Mth transistor are mirror-symmetrical with respect to the second symmetry axis;
the first scan signal line is connected to gate electrodes of the first transistor to the Mth transistor respectively; the second scan signal line is electrically connected to gate electrodes of the M+1th transistor to the 2Mth transistor respectively, and the first scan signal line and the second scan signal line are mirror-symmetrical with respect to the second symmetry axis and are located at a first side and a second side of the optical filter respectively, the first side and the second side being opposite to each other; and
the M data signal lines are located at a third side of the optical filter, the third side being different from the first side and the second side, and a jth data signal line is electrically connected to source electrodes of the jth transistor and the j+Mth transistor respectively, M≥1, 1≤i≤2M, and 1≤j≤M.

7. The display panel according to claim 6 , wherein all pixel electrodes in each sub-pixel are arranged in a same layer; and
a distance between the second connecting portions of adjacent pixel electrodes is 1.4 microns to 1.6 microns.

8. The display panel according to claim 6 , wherein in each sub-pixel, a pixel electrode of an odd ordinal number is arranged in a different layer from a pixel electrode of an even ordinal number;
a spacing between an orthographic projection of the ith pixel electrode on the first base substrate and an orthographic projection of an i+1th pixel electrode on the first base substrate is equal to 0;
the first substrate further comprises a first planarization layer and a second planarization layer; the first planarization layer is located on one side of the array structure layer away from the first base substrate, and the second planarization layer is located on one side of the first planarization layer away from the first base substrate;
the pixel electrode of an odd ordinal number is located between the first planarization layer and the second planarization layer, and the pixel electrode of an even ordinal number

Assignees

• Boe Technology Group Co Ltd

Inventors

• Li Zhongxiao
• Zhao Wenqing
• Zhang Hui

Classifications

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/136209

  Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

• G02B27/0093

  with means for monitoring data relating to the user, e.g. head-tracking, eye-tracking · CPC title

• G02F1/136222

  Colour filters incorporated in the active matrix substrate · CPC title

• G02B3/0037

  characterized by the distribution or form of lenses · CPC title