Anti-fuse readout circuit, anti-fuse memory, and testing method

Patent metadata

Field	Value
Publication number	US-12082402-B2
Application number	US-202217828017-A
Country	US
Kind code	B2
Filing date	May 30, 2022
Priority date	Dec 24, 2021
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

An anti-fuse readout circuit, an anti-fuse memory, and a testing method are provided. The anti-fuse readout circuit includes: a latch circuit configured to latch data read out from an anti-fuse storage array; and a transmission circuit connected to an output terminal of the latch circuit, the transmission circuit being configured to transmit data latched in the latch circuit to a data port in response to a read test command.

First claim

What is claimed is:

1. An anti-fuse readout circuit, comprising:
a latch circuit configured to latch data read out from an anti-fuse storage array; and
a transmission circuit connected to an output terminal of the latch circuit, the transmission circuit being configured to transmit data latched in the latch circuit to a data port in response to a read test command; and,
wherein the latch circuit comprises:
a multichannel latch subcircuit, each channel of the latch subcircuit being configured to latch one bit of data in the data read out from the anti-fuse storage array;
the transmission circuit comprises:
a plurality of transmission subcircuits, each of the plurality of transmission subcircuits being connected to an output terminal of the latch subcircuit, and each of the plurality of transmission subcircuits being configured to respectively transmit, in response to different read test commands, the one bit of data latched in the latch subcircuit to the data port;
wherein the latch subcircuit comprises:
a first switch transistor configured to receive the one bit of data, the first switch transistor being enabled in response to a location strobe signal, such that an output terminal of the first switch transistor outputs the one bit of data; and
a latch circuit, an output terminal of the latch circuit being connected to each of the plurality of transmission subcircuits, and an input terminal of the latch circuit being connected to the output terminal of the first switch transistor.

2. The anti-fuse readout circuit according to claim 1 , wherein the first switch is a first transmission gate, a first control terminal of the first transmission gate being configured to receive the location strobe signal, and an input terminal of the first transmission gate being configured to receive the one bit of data; and
the latch subcircuit further comprises: a first inverter, an input terminal of the first inverter being configured to receive the location strobe signal, and an output terminal of the first inverter being connected to a second control terminal of the first transmission gate.

3. The anti-fuse readout circuit according to claim 1 , wherein each of the plurality of transmission subcircuits comprises a second switch transistor, the second switch transistor being enabled in response to the read test command, to transmit the one bit of data to the data port.

4. The anti-fuse readout circuit according to claim 3 , wherein the second switch transistor comprises a second transmission gate, a first control terminal of the second transmission gate being configured to receive the read test command, and an input terminal of the second transmission gate being configured to receive the one bit of data; and
each of the plurality of transmission subcircuits further comprises: a second inverter, an input terminal of the second inverter being configured to receive the read test command, and an output terminal of the second inverter being connected to a second control terminal of the second transmission gate.

5. The anti-fuse readout circuit according to claim 1 , further comprising:
a buffer circuit arranged between an output terminal of the transmission circuit and the data port.

6. The anti-fuse readout circuit according to claim 5 , wherein the buffer circuit comprises even number of inverters connected in series, an input terminal of the inverter in the first location being connected to the output terminal of the transmission circuit, and an output terminal of the inverter in the last location being connected to the data port.

7. The anti-fuse readout circuit according to claim 1 , further comprising:
a comparison circuit connected to the output terminal of the latch circuit, the comparison circuit being configured to compare whether the data latched in the latch circuit matches current address information.

8. The anti-fuse readout circuit according to claim 7 , wherein the comparison circuit comprises an XNOR gate, an input terminal of the XNOR gate being connected to the output terminal of the latch circuit, and other input terminal of the XNOR gate being configured to receive the current address information.

9. The anti-fuse readout circuit according to claim 1 , wherein the transmission circuit is further configured to transmit the data latched in the latch circuit to a same data port.

10. The anti-fuse readout circuit according to claim 1 , wherein the anti-fuse readout circuit comprises a plurality of latch circuits and a plurality of transmission circuits, the anti-fuse readout circuit further comprising:
a selection circuit connected to output terminals of the plurality of transmission circuits, the selection circuit being configured to select a given one of the plurality of transmission circuits to transmit the data from the given transmission circuit to the data port.

11. The anti-fuse readout circuit according to claim 10 , wherein the selection circuit comprises: a plurality of selection output subcircuits, each of the plurality of selection output subcircuits corresponding to one of the plurality of transmission circuits, and the plurality of selection output subcircuits being configured to output the data transmitted by the plurality of transmission circuits in response to a selection signal; and
a switch subcircuit connected between output terminals of the plurality of selection output subcircuits and the data port, the switch subcircuit being configured to transmit the data outputted from the plurality of selection output subcircuits to the data port.

12. The anti-fuse readout circuit according to claim 11 , wherein each of the plurality of selection output subcircuits comprises an AND gate circuit, an input terminal of the AND gate circuit being configured to receive the selection signal, and other input terminal of the AND gate circuit being configured to receive the data outputted from the plurality of transmission circuits.

13. The anti-fuse readout circuit according to claim 11 , wherein the switch subcircuit comprises:
a multistage connected OR gate circuit, each stage of the OR gate circuit corresponding to one of the plurality of selection output subcircuits, and an input terminal of the OR gate circuit being connected to the output terminal of the corresponding one of the plurality of selection output subcircuits; wherein
other input terminal of the OR gate circuit in the first stage is grounded, an output terminal of the OR gate circuit in the last stage being connected to the data port, and the output terminal of the OR gate circuit in the former stage being connected to an input terminal of the OR gate circuit in the latter stage.

14. The anti-fuse readout circuit according to claim 11 , wherein the switch subcircuit comprises:
one OR gate circuit, the output terminals of the plurality of selection output subcircuits all being connected to an input terminal of the OR gate circuit, and an output terminal of the OR gate circuit being connected to the data port.

15. An anti-fuse memory, comprising:
an anti-fuse storage array; and
the anti-fuse readout circuit of claim 1 .

16. A testing method for testing by the anti-fuse readout circuit of claim 1 , the testing method comprising:
reading data from the anti-fuse storage array and latching the data;
transmitting the latched data to the data port in response to the read test command; and
determining whether the data transmitted to the data port meets expectations.

17. The testing method according to claim 16 , wherein the transmitting the latched data to the data port comprises:
in response to

Assignees

• Changxin Memory Tech Inc

Inventors

• Ji Rumin

Classifications

• H10B20/25 Primary

  One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links · CPC title

• G11C17/16

  using electrically-fusible links · CPC title

• G11C29/789

  using non-volatile cells or latches · CPC title

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title