Method for manufacturing memory and memory

Patent metadata

Field	Value
Publication number	US-12082394-B2
Application number	US-202117610433-A
Country	US
Kind code	B2
Filing date	Jul 5, 2021
Priority date	Mar 19, 2021
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

A method for manufacturing a memory includes: providing a substrate, capacitor contact pads being formed in the substrate; forming a laminated structure on the substrate, the laminated structure including a first laminated structure formed on the substrate and a second laminated structure formed on the first laminated structure; forming first through holes in the second laminated structure; forming a protective layer on side walls of the first through holes, the protective layer in the first through holes enclosing second through holes; and etching the first laminated structure along the second through holes to form third through holes, the third through holes exposing the capacitor contact pads.

First claim

What is claimed is:

1. A method for manufacturing a memory, comprising:
providing a substrate, capacitor contact pads being formed in the substrate;
forming a laminated structure on the substrate, the laminated structure comprising a first laminated structure formed on the substrate and a second laminated structure formed on the first laminated structure;
forming first through holes in the second laminated structure;
forming a protective layer on side walls of the first through holes, the protective layer in the first through holes enclosing second through holes; and
etching the first laminated structure along the second through holes to form third through holes, the third through holes exposing the capacitor contact pads;
wherein the laminated structure comprises a plurality of sacrificial layers and a plurality of support layers alternately stacked, a number of the plurality of sacrificial layers is n, and a number of the plurality of support layers is n+1, wherein n is a positive integer greater than or equal to 2;
the first laminated structure and the second laminated structure each comprise at least one sacrificial layer.

2. The method for manufacturing a memory according to claim 1 , wherein the first through holes penetrate a plurality of sacrificial layers, a number of the plurality of sacrificial layers is i, and the third through holes penetrate the remaining plurality of sacrificial layers, a number of the remaining plurality of sacrificial layers is n−i, wherein i is a positive integer greater than or equal to 1 and less than n.

3. The method for manufacturing a memory according to claim 1 , wherein widths of the third through holes are equal to widths of the second through holes.

4. The method for manufacturing a memory according to claim 3 , wherein the etching the first laminated structure along the second through holes to form third through holes:
the etching gas comprises C 4 F 8 , O 2 and Ar, the etching selection ratio of the sacrificial layers to the protective layer is greater than 100, and the ratio of the longitudinal etching rate of the sacrificial layers to the lateral etching rate of the sacrificial layers is greater than 100.

5. The method for manufacturing a memory according to claim 1 , wherein widths of the third through holes are equal to widths of the first through holes.

6. The method for manufacturing a memory according to claim 5 , wherein the etching the first laminated structure along the second through holes to form third through holes:
the etching gas comprises C 4 F 8 , C 4 F 6 and O 2 , and the ratio of the etching rate of the sacrificial layers to the etching rate of the protective layer is 5 to 20;
or, the etching gas comprises C 4 F 8 , O 2 and Ar, the etching selection ratio of the sacrificial layers to the protective layer is greater than 100, and the ratio of the longitudinal etching rate of the sacrificial layers to the lateral etching rate of the sacrificial layers is 20 to 50.

7. The method for manufacturing a memory according to claim 1 , wherein the protective layer is formed by atomic layer deposition.

8. The method for manufacturing a memory according to claim 1 , wherein material of the protective layer comprises polysilicon.

9. The method for manufacturing a memory according to claim 1 , wherein the laminated structure comprises a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer and a third support layer sequentially stacked, and the first support layer is located on the substrate.

10. The method for manufacturing a memory according to claim 9 , wherein the forming first through holes in the second laminated structure comprises:
forming the first through holes in the second laminated structure, the first through holes penetrating the third support layer and the second sacrificial layer, and the first through holes being opposite to the capacitor contact pads.

11. The method for manufacturing a memory according to claim 10 , wherein the etching the first laminated structure along the second through holes to form third through holes comprises:
etching the first laminated structure along the second through holes to form the third through holes penetrating the second support layer, the first sacrificial layer and the first support layer, the third through holes being in contact with the capacitor contact pads.

12. The method for manufacturing a memory according to claim 10 , wherein the forming the first through holes in the second laminated structure comprises:
forming a mask on the second laminated structure, etching holes being formed in the mask; and
etching the third support layer and the second sacrificial layer along the etching holes to form the first through holes.

13. The method for manufacturing a memory according to claim 12 , wherein the forming a protective layer on side walls of the first through holes comprises:
depositing the protective layer on the side walls and bottom walls of the first through holes, side walls of the etching holes, and a surface of the mask; and
removing the protective layer on bottoms of the first through holes and the surface of the mask.

14. The method for manufacturing a memory according to claim 13 , wherein the protective layer on bottoms of the first through holes is removed by a plasma etching process, the power of the plasma etching process is greater than 10000 watts, and the frequency is less than or equal to 2 MHz.

15. The method for manufacturing a memory according to claim 13 , wherein a material of the mask is the same as a material of the protective layer.

16. The method for manufacturing a memory according to claim 12 , wherein the mask comprises a polysilicon layer formed on the second laminated structure and an oxide layer formed on the polysilicon layer;
the etching the third support layer and the second sacrificial layer along the etching holes further comprises: removing the oxide layer and part of the polysilicon layer.

17. The method for manufacturing a memory according to claim 16 , wherein after the etching the first laminated structure along the second through holes to form third through holes, the method for manufacturing a memory further comprises:
removing the polysilicon layer;
or, removing the polysilicon layer and the protective layer in the etching holes and the first through holes.

18. A memory, wherein the memory is provided with capacitor holes, the capacitor holes comprise first through holes and third through holes communicated with the first through holes, and the first through holes and the third through holes are formed by the method for manufacturing a memory according to claim 1 .

Assignees

• Changxin Memory Tech Inc

Inventors

• Liu Tao
• Xia Jun
• Zhan Kangshu
• Li Sen
• Wan Qiang
• Xu Penghui

Classifications

• H10B12/033

  the capacitor extending over the transistor · CPC title

• H10B12/03 Primary

  Making the capacitor or connections thereto · CPC title

• H10B12/30

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• H10B12/05 Primary

  Making the transistor · CPC title