Method for manufacturing memory and memory

Patent metadata

Field	Value
Publication number	US-12082393-B2
Application number	US-202117457819-A
Country	US
Kind code	B2
Filing date	Dec 6, 2021
Priority date	Feb 5, 2021
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

A method for manufacturing a memory and a memory is provided. The method for manufacturing a memory includes: providing a substrate; stacking an electrode support structure, a protective layer and a first mask layer in sequence on the substrate; patterning the first mask layer on an array region, and etching the protective layer, the electrode support structure and the substrate by using the patterned first mask layer as a mask, to form capacitor holes penetrating the protective layer and the electrode support structure and extending into the substrate; removing the first mask layer; and forming a first electrode layer on side walls and bottom walls of the capacitor holes, a top surface of the first electrode layer being flush with a top surface of the electrode support structure.

First claim

The invention claimed is:

1. A method for manufacturing a memory, comprising:
providing a substrate, the substrate comprising an array region and a peripheral circuit region connected to the array region;
stacking an electrode support structure, a protective layer and a first mask layer in sequence on the substrate;
patterning first mask layer on the array region, and etching the protective layer, the electrode support structure and the substrate by using the patterned first mask layer as a mask, to form capacitor holes penetrating the protective layer and the electrode support structure and extending into the substrate;
removing the first mask layer; and
forming a first electrode layer on side walls and bottom walls of the capacitor holes, a top surface of the first electrode layer being flush with a top surface of the electrode support structure.

2. The method for manufacturing the memory according to claim 1 , wherein in the stacking the electrode support structure, the protective layer and the first mask layer in sequence on the substrate, the first mask layer comprises a polysilicon layer, an oxide layer and a first hard mask layer sequentially stacked on the protective layer, and a thickness of the polysilicon layer is 5 to 7 times a thickness of the protective layer.

3. The method for manufacturing the memory according to claim 2 , wherein the protective layer has the thickness of 50 nm to 110 nm, and a material of the protective layer is silicon oxide.

4. The method for manufacturing the memory according to claim 3 , wherein in the stacking the electrode support structure, the protective layer and the first mask layer in sequence on the substrate, the electrode support structure comprises a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer and a third support layer sequentially stacked on the substrate.

5. The method for manufacturing the memory according to claim 4 , wherein the patterning the first mask layer on the array region comprises:
patterning first hard mask layer on the array region, and etching the oxide layer and the polysilicon layer by using a patterned first hard mask layer as a mask, to form a patterned oxide layer and a patterned polysilicon layer; and
etching the protective layer, the third support layer, the second sacrificial layer, the second support layer, the first sacrificial layer, the first support layer and the substrate by using the patterned oxide layer and the patterned polysilicon layer as masks, to form a plurality of electrode support portions spaced apart on the array region, the adjacent electrode support portions constituting the capacitor holes.

6. The method for manufacturing the memory according to claim 5 , wherein the removing the first mask layer comprises:
removing the polysilicon layer by dry etching, an etching gas for the dry etching being one of HBr, NF 3 and O 2 , and a dry etching temperature being between 30° C. and 90° C.

7. The method for manufacturing the memory according to claim 4 , after the forming the first electrode layer on side walls and bottom walls of the capacitor holes, the method for manufacturing further comprising:
forming a second mask layer on the protective layer above the array region;
patterning the second mask layer to form a plurality of first openings spaced apart in the second mask layer, each of the first openings exposing at least one of a plurality of electrode support portions, and each of the first openings having a preset projection region on the substrate;
removing the third support layer in the electrode support portions that is exposed in the first openings to expose the second sacrificial layer; and removing the protective layer and the third support layer on the peripheral circuit region.

8. The method for manufacturing the memory according to claim 7 , after the removing the third support layer in the electrode support portions that is exposed in the first openings, and removing the protective layer and the third support layer on the peripheral circuit region, the method for manufacturing further comprising:
removing the protective layer on the array region and the second sacrificial layer on the array region and the peripheral circuit region by wet etching.

9. The method for manufacturing the memory according to claim 8 , wherein an etching solution used in the wet etching is a mixed solution of NH 4 F and HF.

10. The method for manufacturing the memory according to claim 8 , before the removing the protective layer on the array region and the second sacrificial layer on the array region and the peripheral circuit region by wet etching, and after the removing the third support layer in the electrode support portions that is exposed in the first openings, the method for manufacturing further comprising:
removing the second mask layer by dry etching.

11. The method for manufacturing the memory according to claim 10 , wherein in the removing the second mask layer by dry etching, a gas for dry etching comprises at least one of Cl 2 , SO 2 , C 4 F 6 , CH 2 F 2 , O 2 , CF 4 , CHF 3 and SF 6 .

12. The method for manufacturing the memory according to claim 10 , after the removing the protective layer on the array region and the second sacrificial layer on the array region and the peripheral circuit region by wet etching, the method for manufacturing further comprising:
forming a third mask layer on the third support layer in the array region;
patterning the third mask layer to form a plurality of second openings arranged spaced apart in the third mask layer, a projection region of each of the second openings on the substrate coincides with the preset projection region;
removing the second support layer in the electrode support portions that is exposed in the second openings, to expose the first sacrificial layer; and removing the second support layer on the peripheral circuit region.

13. The method for manufacturing the memory according to claim 12 , after the removing the second support layer in the electrode support portions that is exposed in the second openings, and removing the second support layer on the peripheral circuit region, the method for manufacturing further comprising:
removing the third mask layer; and
removing the first sacrificial layer by wet etching.

14. The method for manufacturing the memory according to claim 12 , wherein the second mask layer and the third mask layer each comprise a second hard mask layer and a photoresist layer stacked, and the second hard mask layer is arranged on the protective layer.

15. The method for manufacturing the memory according to claim 1 , wherein the forming the first electrode layer on the side walls and the bottom walls of the capacitor holes, the top surface of the first electrode layer being flush with the top surface of the electrode support structure comprises:
forming a conductive layer on the side walls and the bottom walls of the capacitor holes and on a top surface of the protective layer; and
removing the conductive layer on the top surface of the protective layer and part of the conductive layer on the side walls of the capacitor holes, the conductive layer remaining on the side walls and the bottom walls of the capacitor holes constituting the first electrode layer.

Assignees

• Changxin Memory Tech Inc

Inventors

• Wan Qiang
• Xia Jun
• Zhan Kangshu
• Li Sen
• Liu Tao
• Xu Penghui

Classifications

• H10D1/716 Primary

  having vertical extensions · CPC title

• H10B12/50

  Peripheral circuit region structures · CPC title

• H10B12/30

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• H10B12/09

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title

• H10B12/03 Primary

  Making the capacitor or connections thereto · CPC title