DC balanced transition encoding

Patent metadata

Field	Value
Publication number	US-12081376-B2
Application number	US-202217831354-A
Country	US
Kind code	B2
Filing date	Jun 2, 2022
Priority date	Nov 5, 2021
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

A system and method for DC balanced transition encoding. In some embodiments, the method includes: generating a set of candidate encoding keys for a set of raw data words; selecting a first encoding key, of the set of candidate encoding keys, based on a first disparity contribution; and encoding the raw data words with the first encoding key, the first disparity contribution being a difference between the number of ones and the number of zeros in the result of encoding the set of raw data words with the first encoding key.

First claim

What is claimed is:

1. A method, comprising:
generating a set of candidate encoding keys for a set of raw data words;
selecting a first encoding key, of the set of candidate encoding keys, based on a first disparity contribution; and
encoding the raw data words with the first encoding key to form a result comprising a number of ones and a number of zeros,
wherein the first disparity contribution is a difference between the number of ones and the number of zeros in the result of encoding the set of raw data words with the first encoding key.

2. The method of claim 1 , wherein the selecting of the first encoding key is further based on a running disparity of previously generated encoded data words.

3. The method of claim 2 , wherein:
an absolute value of a sum of:
the running disparity of previously generated encoded data words and
the first disparity contribution

is less than the absolute value of the sum of:
the running disparity of previously generated encoded data words and
a second disparity contribution; and

the second disparity contribution is a difference between the number of ones and the number of zeros in the result of encoding the set of raw data words with a second encoding key of the set of candidate encoding keys.

4. The method of claim 2 , further comprising calculating the first disparity contribution, wherein the calculating of the first disparity contribution comprises:
calculating a set of bit level disparities, each corresponding to a bit level of the raw data words;
changing a sign of each bit level disparity corresponding to a one in the first encoding key, to form a set of polarity-adjusted bit level disparities; and
summing:
the polarity-adjusted bit level disparities; and
a disparity of the first encoding key,

wherein:
an absolute value of the bit level disparity at each bit level is equal to the absolute value of the difference between
the number of ones, at the bit level, in all of the raw data words, and
the number of zeros at the bit level, in all of the raw data words; and

the absolute value of the disparity of the first encoding key is equal to the absolute value of the difference between the number of ones of the first encoding key and the number of zeros of the first encoding key.

5. The method of claim 4 , wherein the calculating of a bit level disparity, of the set of bit level disparities, at a first bit level, comprises calculating the difference between
twice the number of ones at the first bit level and
the number of raw data words.

6. The method of claim 1 , wherein the result of encoding the set of raw data words with the first encoding key comprises:
the first encoding key; and
an exclusive-OR of the first encoding key with each the raw data words.

7. The method of claim 1 , wherein the result of encoding the set of raw data words with the first encoding key is a set of encoded data words having a maximum run length not exceeding a first threshold.

8. The method of claim 7 , wherein the result of encoding the set of raw data words with the first encoding key comprises:
the first encoding key; and
an exclusive-OR of the first encoding key with each the raw data words.

9. The method of claim 7 , wherein the result of encoding the set of raw data words with any one of the set of candidate encoding keys is a set of encoded data words having a maximum run length not exceeding the first threshold.

10. The method of claim 1 , wherein an absolute value of the first disparity contribution is less than an absolute value of a second disparity contribution; and
the second disparity contribution is a difference between the number of ones and the number of zeros in the result of encoding the set of raw data words with a second encoding key of the set of candidate encoding keys.

11. A system, comprising:
a processing circuit; and
a memory connected to the processing circuit,
the memory storing instructions that, when executed by the processing circuit, cause the system to perform a method, the method comprising:
generating a set of candidate encoding keys for a set of raw data words;
selecting a first encoding key, of the set of candidate encoding keys, based on a running disparity of previously generated encoded data words; and
encoding the raw data words with the first encoding key to form a result comprising a number of ones and a number of zeros.

12. The system of claim 11 , wherein the selection of the first encoding key is further based on a first disparity contribution, the first disparity contribution being a difference between the number of ones and the number of zeros in the result of encoding the set of raw data words with the first encoding key.

13. The system of claim 12 , wherein:
an absolute value of a sum of:
the running disparity of previously generated encoded data words and
the first disparity contribution

is less than the absolute value of the sum of:
the running disparity of previously generated encoded data words and
a second disparity contribution; and

the second disparity contribution is a difference between the number of ones and the number of zeros in the result of encoding the set of raw data words with a second encoding key of the set of candidate encoding keys.

14. The system of claim 12 , wherein the method comprises calculating the first disparity contribution, wherein the calculating of the first disparity contribution comprises:
calculating a set of bit level disparities, each corresponding to a bit level of the raw data words;
changing the sign of each bit level disparity corresponding to a one in the first encoding key, to form a set of polarity-adjusted bit level disparities; and
summing:
the polarity-adjusted bit level disparities; and
a disparity of the first encoding key,

wherein:
the absolute value of the bit level disparity at each bit level is equal to the absolute value of the difference between
the number of ones, at the bit level, in all of the raw data words, and
the number of zeros at the bit level, in all of the raw data words; and

the absolute value of the disparity of the first encoding key is equal to the absolute value of the difference between the number of ones of the first encoding key and the number of zeros of the first encoding key.

15. The system of claim 14 , wherein the calculating of a bit level disparity, of the set of bit level disparities, at a first bit level, comprises calculating the difference between twice the number of ones at the first bit level and the number of raw data words.

16. The system of claim 11 , wherein the result of encoding the set of raw data words with the first encoding key comprises:
the first encoding key; and
an exclusive-OR of the first encoding key with each the raw data words.

17. The system of claim 11 , wherein the result of encoding the set of raw data words with the first encoding key is a set of encoded data words having a maximum run length less than a first threshold.

18. The system of claim 17 , wherein the result of encoding the set of raw data words with the first encoding key comprises:
the first encoding key; and
an exclusive-OR of the first encoding key with each the raw data words.

19. The system of claim 17 , wherein the result of encoding the set of raw data words with any one of the set of candidate encoding keys is a set of encoded data words having a maximum run length less than the first threshold.

20. A display, comprising:
a timing controller; and
a driver integrated circ

Assignees

• Samsung Display Co Ltd

Inventors

• Abbasfar Aliazam

Classifications

• H04L25/45

  using electronic distributors · CPC title

• H04L9/0662

  with particular pseudorandom sequence generator · CPC title

• H03M99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H04L7/0008

  Synchronisation information channels, e.g. clock distribution lines · CPC title

• H03M7/20

  Conversion to or from n-out-of-m codes · CPC title