Circuits and methods of detecting at least partial breakdown of canary circuits

Patent metadata

Field	Value
Publication number	US-12080378-B2
Application number	US-202217709076-A
Country	US
Kind code	B2
Filing date	Mar 30, 2022
Priority date	Mar 30, 2022
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

According to one implementation of the present disclosure, a circuit comprises: a memory array comprising one or more groupings of bitcells, one or more bitlines, and one or more wordlines; and one or more canary circuits coupled to the memory array, wherein each of the canary circuits is configured to predict at least partial breakdown of a corresponding grouping of bitcells in the memory array. According to one implementation of the present disclosure, a method includes: providing an excitation stress on one or more canary circuits corresponding to a grouping of bitcells in a memory array; detecting at least a partial breakdown of the one or more canary circuits; and generating a flag.

First claim

What is claimed is:

1. A circuit comprising:
a memory array comprising one or more groupings of bitcells, one or more bitlines, and one or more wordlines; and
one or more canary circuits coupled to the memory array, wherein each of the canary circuits is configured to predict at least partial breakdown of a corresponding grouping of bitcells in the memory array, and
wherein each of the one or more canary circuits are activated by a substantially similar wordline voltage, wherein the wordline voltage is a negative voltage, wherein an absolute value of the negative voltage is less than a voltage threshold, and wherein the voltage threshold corresponds to a rate of voltage discharge of a bitline to allow a time-to-digital converter (TDC) or counter to detect a breakdown of at least one of the one or more canary circuits.

2. The circuit of claim 1 , wherein the one or more canary circuits comprise one or more columns of canary circuits, and wherein each of the one or more columns of canary circuits is configured to predict the at least partial breakdown of the corresponding grouping of bitcells at respective one or more different time intervals in the memory array.

3. The circuit of claim 1 , wherein the one or more canary circuits comprise one or more rows of canary circuits, and wherein each of the one or more rows of canary circuits is configured to predict the at least partial breakdown of a corresponding bitcell or one or more rows of bitcells in the memory array.

4. The circuit of claim 1 , wherein: the at least partial breakdown comprises a range of the breakdown of the corresponding grouping of bitcells in the memory array, wherein the range of breakdown comprises: a degradation of one or more access devices of at least a portion of the grouping of bitcells, and
each of the one or more canary circuits is configured to predict the range of the breakdown of respective one or more access devices in bitcells of the portion of the grouping of bitcells.

5. The circuit of claim 4 , wherein:
the range of the degradation comprises: an anticipation of an irreversible short-circuit in one insulating gate oxide of solely one access device in the bitcells to a full breakdown of the grouping of bitcells;
each of the groupings of bitcells comprises: a memory bank, a memory block, one or more rows of bitcells, or one or more columns of bitcells, or a single bitcell.

6. The circuit of claim 1 , wherein each of the one or more canary circuits comprises:
a first selector device; and
a load, wherein the load is approximately matched to a corresponding load of the grouping of bitcells.

7. The circuit of claim 6 , wherein each of the one or more canary circuits comprises:
a second selector device coupled in series to the first selector device, wherein the second selector device is configured to control activation of a respective canary circuit and enable decoupling from a respective wordline of the one or more wordlines.

8. The circuit of claim 6 , wherein the load comprises a first inverter, and further comprising:
a second selector device; and
a second inverter, wherein the first selector device comprises a gate oxide layer with a thickness less than 10 nanometers.

9. The circuit of claim 1 , wherein the one or more canary circuits comprise one or more columns of canary circuits, and further comprising:
for each column of canary circuits:
stress driver circuitry;
precharge circuitry;
circuitry configured to control a gate signal to select between the stress driver circuit or the precharge circuitry based on a control signal; and
a comparator.

10. The circuit of claim 9 , further comprising:
a time-to-digital converter (TDC) or counter, wherein the TDC or counter is programmable based on one or more predetermined canary characteristics and a quantity of the canary circuits.

11. The circuit of claim 1 , further comprising:
a canary control circuit configured to:
transmit one or more control signals to: activate respective write driver circuits or precharge circuits of one or more columns or rows of the canary circuits;
detect a discharge voltage of the one or more bitlines; or
receive an output signal, from one or more: comparators, a time-to-digital converter (TDC), or counters, wherein the output signal corresponds to the partial breakdown of one or more canary circuits.

12. The circuit of claim 11 , wherein the canary control circuit is configured to:
generate a flag, wherein the flag corresponds to:
providing an interruption or notification;
replicating data in the memory array corresponding to the one or more canary circuits in a different memory array;
indicating a particular grouping of bitcells as malfunctioning; or
providing for the memory array to operate at a lower operate voltage.

13. The circuit of claim 1 , wherein each column of the one or more canary circuits is configured to detect failure of the corresponding grouping of bitcells at a respective different time interval.

14. The circuit of claim 1 , wherein:
respective columns of the two or more canary circuits are configured to detect the at least partial breakdown for respective different time intervals; and
each different voltage provided to the respective columns corresponds to the respective different time intervals.

15. The circuit of claim 1 , wherein:
the memory array comprises an SRAM or a DRAM; or
the memory array comprises non-volatile memory, and wherein the non-volatile memory comprises one of flash memory, ferroelectric random-access memory (FeRAM), magnetic random-access memory (MRAM), phase-change memory (PCM), and resistive random-access memory (RRAM).

16. A method comprising:
providing an excitation stress on one or more canary circuits corresponding to a grouping of bitcells in a memory array, wherein providing the excitation stress comprises one of: controlling electrical amplitude or pulse widths of a bitline voltage or a wordline voltage coupled to the one or more canary circuits;
detecting at least a partial breakdown of the one or more canary circuits; and
generating a flag.

17. The method of claim 16 , wherein the bitline voltage is controlled, wherein:
controlling the electrical amplitude comprises one of:
increasing the bitline voltage above a supply voltage, or
decreasing the bitline voltage below a ground voltage; and wherein;

controlling the pulse widths comprises increasing a pulse width of the bitline voltage for a duration longer than a threshold voltage time duration; or
controlling a bitline current for a duration longer than a threshold current time duration.

18. The method of claim 16 , wherein the wordline voltage is controlled, wherein:
controlling the electrical amplitude comprises one of:
increasing the wordline voltage above a supply voltage, or
decreasing the wordline voltage below a ground voltage; and wherein:

controlling the pulse widths comprises increasing a pulse width of the wordline voltage for a duration longer than a threshold voltage time duration; or
controlling a wordline current for a duration longer than a threshold current time duration.

19. A circuit comprising:
a memory array comprising one or more groupings of bitcells, one or more bitlines, and one or more wordlines;
one or more canary circuits coupled to the memory array; and
a canary control circuit configured to induce at least partial breakdown of the one or more canary circuits to predict degradation of the memory array.

Assignees

• Advanced Risc Mach Ltd

Inventors

• García Redondo Fernando
• Prabhat Pranay
• Bhargava Mudit
• Jeloka Supreet

Classifications

• G11C7/16

  Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C5/12

  Apparatus or processes for interconnecting storage elements, e.g. for threading magnetic cores · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C29/50

  Marginal testing, e.g. race, voltage or current testing · CPC title