System and method for accelerated ray tracing with asynchronous operation and ray transformation

Patent metadata

Field	Value
Publication number	US-12079920-B2
Application number	US-202218052147-A
Country	US
Kind code	B2
Filing date	Nov 2, 2022
Priority date	Aug 20, 2020
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

A graphics processing unit (GPU) includes one or more processor cores adapted to execute a software-implemented shader program, and one or more hardware-implemented ray tracing units (RTU) adapted to traverse an acceleration structure to calculate intersections of rays with bounding volumes and graphics primitives asynchronously with shader operation. The RTU implements traversal logic to traverse the acceleration structure including transformation of rays as needed to account for variations in coordinate space between levels, stack management, and other tasks to relieve burden on the shader, communicating intersections to the shader which then calculates whether the intersection hit a transparent or opaque portion of the object intersected. Thus, one or more processing cores within the GPU perform accelerated ray tracing by offloading aspects of processing to the RTU, which traverses the acceleration structure within which the 3D environment is represented.

First claim

What is claimed is:

1. A method for graphics processing, comprising:
executing a shader program that performs ray tracing;
using a hardware-implemented ray tracing unit (RTU) that traverses an acceleration structure at the request of the shader program; and
using, at the shader program, results of the acceleration structure traversal;
wherein the shader program is configured to send root node and information related to rays to the RTU which is configured to traverse the acceleration structure, with the shader program being configured for reading at least one status of the RTU and the RTU reporting at least a first status as it continues its traversal, the shader program passing hit identifications to the RTU to enable the RTU to shorten rays, at least a second status from the RTU indicating that the RTU has found an intersection with a first primitive, the shader program performing hit testing and responsive to finding that the first primitive was hit by a ray, informs the RTU of the hit.

2. The method of claim 1 , wherein using the results comprises shading pixels in computer-generated graphics.

3. The method of claim 1 , wherein the results of the acceleration structure traversal by the RTU include the detection of intersection between a first ray and bounding volumes contained within the acceleration structure, and/or intersection between a second ray and primitives contained within the acceleration structure.

4. The method of claim 3 , wherein the results of the acceleration structure traversal by the RTU include detection of the earliest intersection between a first ray and primitives contained within the acceleration structure.

5. The method of claim 1 , wherein the RTU processing includes maintenance of a stack used in the acceleration structure traversal.

6. The method of claim 1 , wherein the results of the acceleration structure traversal by the RTU include a sorting by the RTU of the intersections detected by the RTU, by distance of the intersections from ray origin, such that:
the RTU detects a first intersection between a first ray and a primitive as it traverses the acceleration structure; and
the RTU detects a second intersection between the first ray and a primitive as it traverses the acceleration structure; and
when communicating results from the RTU to the shader program, the second intersection result is communicated before the first intersection result, which also is communicated to the shader program.

7. A graphic processing unit (GPU) comprising:
at least one processor core adapted to execute a software-implemented shader; and
at least one ray tracing unit (RTU) adapted to identify intersections of rays with objects to generate results and return the results to the shader, the shader being configured for receiving a first status that the RTU has found an intersection with a first primitive, the shader configured for performing hit testing on the first primitive and responsive to determining the first primitive was hit by the ray, the shader being configured for informing the RTU, the RTU being configured for determining intersections with second and third primitives, the third primitive being closer to a ray origin than the second primitive, the shader being configured for accessing RTU information to perform hit testing on the third primitive and not on the second primitive.

8. The GPU of claim 7 , wherein the RTU comprises hardware circuitry to identify the intersections and the shader is adapted to identify the hits using software.

9. The GPU of claim 7 , wherein the shader is configured with instructions executable by the processor core to shade pixels in three dimensional (3D) computer graphics.

10. The GPU of claim 7 , wherein the RTU comprises hardware circuitry to implement stack management of a stack used in traversal of an acceleration structure.

11. The GPU of claim 7 , wherein the RTU comprises hardware circuitry to transform at least a first ray from world space to a coordinate space corresponding to a lower level of a multi-level acceleration structure.

12. The GPU of claim 7 , wherein the RTU comprises hardware circuitry to transform at least a first ray from a coordinate space corresponding to a lower level of a multi-level acceleration structure to world space.

13. A method for graphics processing, comprising:
executing, on a processing unit (PU), a shader program that performs ray tracing of a three dimensional (3D) environment represented by a data structure;
using a hardware-implemented unit (HIU) that traverses the data structure at the request of the shader program; and
using, at the shader program, results of traversal of the data structure by the HIU, wherein the HIU identifies intersections of rays with elements in the data structure and reports the intersections to the shader program for the shader program to determine hits for all nodes, such that the shader program performs hit testing for all nodes, determining whether a ray passed through a transparent portion of an element or hit a non-transparent portion of the element.

14. The method of claim 13 , wherein data structure traversal by the HIU is asynchronous with respect to the shader program.

15. The method of claim 13 , wherein the results of data structure traversal by the HIU include the detection of intersection between a ray and bounding volumes contained within the data structure.

16. The method of claim 13 , wherein the HIU maintains a stack used in the data structure traversal.

17. The method of claim 13 , wherein the data structure comprises a hierarchy with a plurality of levels.

18. The method of claim 17 , wherein the results of data structure traversal by the HIU include detection of a transition from a higher level to a lower level within the plurality of levels of the data structure.

19. The method of claim 17 , wherein the results of data structure traversal by the HIU include detection of a transition from a lower level to a higher level within the plurality of levels of the data structure.

20. The method of claim 17 , wherein traversal of the data structure traversal by the HIU includes handling of transitions between the plurality of levels of the data structure.

Assignees

• Sony Interactive Entertainment LLC

Inventors

• Cerny Mark Evan

Classifications

• G06T15/80

  Shading · CPC title

• G06T15/005

  General purpose rendering architectures · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T2200/28

  involving image processing hardware · CPC title

• G06T15/50

  Lighting effects · CPC title