Virtual processor system and method utilizing discrete component elements

Patent metadata

Field	Value
Publication number	US-12079650-B2
Application number	US-202016875016-A
Country	US
Kind code	B2
Filing date	May 15, 2020
Priority date	May 15, 2020
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

A system and method for the dynamic, run-time configuration of logic core register files, and the provision of an associated execution context. The dynamic register files as well as the associated execution context information are software-defined so as to be virtually configured in random-access memory. This virtualization of both the processor execution context and register files enables the size, structure and performance to be specified at run-time and tailored to the specific processing, instructions and data associated with a given processor state or thread, thereby minimizing both the aggregate memory required and the context switching time. In addition, the disclosed system and method provides for processor virtualization which further enhances the flexibility and efficiency.

First claim

What is claimed is:

1. A computer system including a processor and memory configured to define a component-based virtual processor comprising:
the processor configured to generate within the memory;
at least one virtual execution context element comprising information defining a particular processor state and at least one set of executable instructions, wherein the information defining the particular processor state and the at least one set of executable instructions is stored in a specific portion of a first addressable memory having a capacity configured by the processor at run-time to be equal to a memory space required to store the information defining the particular processor state and the at least one-set of executable instructions; and
at least one virtual processor base element comprising information stored in at least one specific portion of a second addressable memory, the stored information defining at least one base register pointer, wherein the at least one base register pointer comprises at least one memory address enabling the at least one virtual processor base element to access the specific portion of the first addressable memory storing the information defining the particular processor state and the at least one set of executable instructions, and wherein a capacity of the at least one specific portion of the second addressable memory is configured by the processor at run-time to be equal to a memory space required to store the information defining the at least one base register pointer.

2. The system of claim 1 further comprising at least one logic cure adapted to execute the at least one set of executable instructions upon the attachment of the at least one virtual processor base element to the at least one virtual execution context element.

3. The system of claim 1 wherein the at least one set of executable instructions comprises a plurality of instructions each of which defines a separate functionality for the component-based virtual processor.

4. The system of claim 1 wherein the base register pointer comprises at least one of the following:
a register context pointer; and
a memory context pointer.

5. The system of claim 1 wherein the first and second addressable memories are both located within a single physical addressable memory.

6. The system of claim 1 wherein at one of the first and second addressable memories comprises at least one of the following:
static random-access memory;
dynamic random-access memory; and
non-volatile memory.

7. The system of claim 1 wherein the at least one set of executable instructions comprises instructions for the initialization of the component-based virtual processor.

8. The system of claim 7 wherein the component-based virtual processor once initialized, is adapted to terminate upon the re-execution of instructions for component-based virtual processor initialization.

9. The system of claim 1 further comprising at least a plurality of additional virtual execution context elements, each comprising information defining an additional processor state and at least one set of additional executable instructions stored in a specific portion of an addressable memory having a capacity based upon the memory space required to store the information defining the additional processor state and the at least one set of additional executable instructions.

10. The system of claim 9 wherein the addressable memory comprises the first addressable memory.

11. The system of claim 9 wherein the at least one base register pointer comprises at least a second memory address associated with at least one of the plurality of additional virtual execution context elements.

12. The system of claim 11 further comprising at least one logic core adapted to execute the at least one set of executable instructions upon the attachment of the at least one virtual processor base element to the at least one virtual execution context element, and thereafter execute a process associated with at least one of the plurality of additional virtual execution context elements.

13. A method of defining a component-based virtual processor comprising:
storing in a specific portion of a first addressable memory at least one virtual execution context element comprising information defining a particular processor state and at least one set of executable instructions, wherein a capacity of the portion of the first addressable memory is configured by the processor at run-time to be equal to a memory space required to store the information defining the particular processor state and the at least one set of executable instructions; and
storing in a specific portion of a second addressable memory at least one virtual processor base element comprising information defining at least one base register pointer, wherein the at least
one base register pointer comprises at least one memory address enabling the at least one virtual processor base element to access the specific portion of the first addressable memory storing the information defining the particular processor slate and the at least one set of executable instructions, and wherein a capacity of the at least one specific portion of the second addressable memory is configured by the processor at run-time to be equal to a memory space required to store the information defining the at least one base register pointer.

14. The method of claim 13 wherein the at least one set of executable instructions comprises a plurality of instructions, each of which defines a separate functionality for the component-based virtual processor.

15. The method of claim 13 wherein the base register pointer comprises at least one of the following:
a register context pointer; and
a memory context pointer.

16. The method of claim 13 wherein the first and second addressable memories are both located within a single physical addressable memory device.

17. The method of claim 13 wherein the addressable memory comprises at least one of the following:
static random-access memory;
dynamic random-access memory; and
non-volatile memory.

18. The method of claim 13 further comprising attaching the at least one virtual processor base element to the at least one virtual execution context element.

19. The method of claim 13 further comprising executing the at least one set of executable instructions utilizing at least one logic core.

20. The method of claim 19 wherein the at least one set of executable instructions comprises instructions for the initialization of the component-based virtual processor.

21. The method of claim 20 further comprising initializing the component-based virtual processor.

22. The method of claim 21 further comprising the step of terminating the component-based virtual processor upon the re-execution of instructions for component-based virtual processor initialization.

Assignees

• Beale Andrew Ward
• Strong David
• Unisys Corp

Inventors

• Beale Andrew Ward
• Strong David

Classifications

• G06F12/06

  Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) · CPC title

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title