High-throughput low-latency hybrid memory module

Patent metadata

Field	Value
Publication number	US-12079486-B2
Application number	US-202318339812-A
Country	US
Kind code	B2
Filing date	Jun 22, 2023
Priority date	Oct 14, 2015
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

First claim

What is claimed is:

1. A method of operating a command buffer device, the method comprising:
receiving one or more local commands from a non-volatile memory controller,
controlling access, by access logic of the command buffer device, to one or more control setting registers by the non-volatile memory controller in a first control mode, wherein a portion of the control setting registers comprises a protected register space;
receiving one or more access commands from the non-volatile memory controller to access the one or more control setting registers; and
interpreting, by an access engine of the command buffer device, the one or more access commands to provide access to the protected register space in the first control mode.

2. The method of claim 1 , wherein interpreting the one or more access commands comprises interpreting the one or more access commands to write to or read from the protected register space.

3. The method of claim 1 , wherein interpreting the one or more access commands comprises interpreting the one or more access commands to provide indirect access to the protected register space.

4. The method of claim 1 , further comprising routing, by the access engine, the one or more access commands to the access logic based at least in part on a mode triggered by a sequence of local commands.

5. The method of claim 1 , wherein the one or more access commands and the local commands are compliant with a physical layer communications protocol.

6. The method of claim 5 , wherein the physical layer communications protocol is a local communication (LCOM) interface protocol.

7. The method of claim 1 , further comprising
receiving one or more host commands from a host memory controller;
issuing one or more dynamic random access memory (DRAM) commands to one or more DRAM devices;
capturing one or more mode register settings from the one or more host commands;
modifying at least one of the one or more mode registered settings based on the one or more local commands to produce one or more modified mode register settings;
generating one or more mode register setting commands based at least in part on the one or more modified mode register settings; and
issuing the one or more mode register setting commands to the one or more DRAM devices.

8. The method of claim 7 , wherein issuing the one or more mode register setting commands comprises issuing the one or more mode register setting commands to the one or more DRAM devices responsive to receiving the one or more local commands.

9. The method of claim 7 , wherein issuing the one or more mode register setting commands comprises issuing the one or more mode register setting commands to the one or more DRAM devices responsive to receiving at least one of a data backup event or a data restore event.

10. The method of claim 7 , further comprising storing the one or more modified mode register settings in the one or more control setting registers.

11. A method of operating a command buffer device, the method comprising:
receiving a host command from a host memory controller,
receiving a local command from a non-volatile memory controller,
controlling access, by access logic of the command buffer device, to a control setting register by the non-volatile memory controller in a first control mode, wherein a portion of the control setting registers comprises a protected register space;
receiving an access command from the non-volatile memory controller to access the control setting register; and
interpreting, by an access engine of the command buffer device, the access command to provide access to the protected register space in the first control mode.

12. The method of claim 11 , wherein interpreting the access command comprises interpreting the access command to write to or read from the protected register space.

13. The method of claim 11 , wherein interpreting the access command comprises interpreting the access command to provide indirect access to the protected register space.

14. The method of claim 11 , further comprising routing, by the access engine, the access command to the access logic based at least in part on a mode triggered by a sequence of local commands.

15. The method of claim 11 , wherein the access command and the local command are compliant with a physical layer communications protocol.

16. The method of claim 15 , wherein the physical layer communications protocol is a local communication (LCOM) interface protocol.

17. The method of claim 11 , further comprising:
capturing a mode register setting from the host command;
modifying the mode registered setting based on the local command to a modified mode register setting;
generating a mode register setting command based at least in part on the modified mode register setting; and
issuing the mode register setting command to one or more dynamic random access memory (DRAM) devices.

18. The method of claim 17 , wherein issuing the mode register setting command comprises issuing the mode register setting command to the one or more DRAM devices responsive to receiving the local command.

19. The method of claim 17 , wherein issuing the mode register setting command comprises issuing the mode register setting command to the one or more DRAM devices responsive to receiving at least one of a data backup event or a data restore event.

20. The method of claim 17 , further comprising storing the modified mode register setting in the control setting register.

Assignees

• Rambus Inc

Inventors

• Shallal Aws
• Miller Micheal
• HORN Stephen

Classifications

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F12/0802

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title