Reconfigurable data processor with fast argument load using a runtime program on a host processor

Patent metadata

Field	Value
Publication number	US-12079157-B2
Application number	US-202318105189-A
Country	US
Kind code	B2
Filing date	Feb 2, 2023
Priority date	Feb 9, 2022
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

Argument registers in a reconfigurable processor are loaded from a runtime program running on a host processor. The runtime program stores a configuration file in a memory. A program load controller reads the configuration file from the memory and distributes it to configurable units in in the reconfigurable processor which sequentially shift it into a shift register of the configuration data store. The runtime program stores an argument load file in the memory and a fast argument load (FAL) controller reads the argument load file from memory and distributes (value, control) tuples to the configuration units in the reconfigurable processor. The configurable units process the tuples by writing the value directly into an argument register made up of a portion of the shift register in the configuration data store specified by the control of the tuple without shifting the value through the shift register.

First claim

The invention claimed is:

1. A reconfigurable processor comprising:
an array of configurable units connected by a bus system, a configurable unit in the array of configurable units including a configuration data store, organized as a shift register, to store configuration data, the configuration data store also including individually addressable argument registers respectively comprising word-sized portions of the shift register adapted to provide arguments to the configurable unit, the configurable unit further including program load logic to receive sub-files of the configuration data via the bus system and to load the received sub-files into the configuration data store by sequentially shifting the received sub-files into the shift register, the configurable unit further including argument load logic to receive argument data via the bus system and load the received argument data into the argument registers without shifting the received argument data through the shift register;
a program load controller associated with the array to respond to a program load command by executing a program load process, including distributing a configuration file comprising the sub-files of configuration data to the configurable unit in the array as specified in the configuration file;
a fast argument load (FAL) controller associated with the array to respond to an FAL command by executing an FAL process, including distributing (value, control) tuples to the configurable unit as specified in an argument load file;
an interface unit in the array of configurable units, the interface unit coupled to the bus system;
an internal network coupled to the interface unit; and
an interface agent coupled between an external interface link and the internal network, to communicate data between the external interface link and the interface unit of the array of configurable units over the internal network, the interface agent configured to communicate with a host processor via the external interface link, and configurable to receive register read and register write requests from a runtime program running on the host processor that are addressed to memory-mapped registers in the interface unit of the array of configurable units and send the register read and register write requests over the internal network to the interface unit of the array of configurable units.

2. The reconfigurable processor of claim 1 , the interface unit including the program load controller and a program load address register writeable by the runtime program running on the host processor to indicate a starting physical memory address of the configuration file to be used by the program load controller.

3. The reconfigurable processor of claim 1 , the interface unit including the FAL controller and an argument load address register writeable by the runtime program running on the host processor to indicate a starting physical memory address of the argument load file to be used by the FAL controller.

4. The reconfigurable processor of claim 3 , the interface unit further including an argument load size register writeable by the runtime program running on the host processor to indicate a file size of the argument load file to be used by the FAL controller.

5. The reconfigurable processor of claim 1 , the interface unit including the program load controller, the FAL controller, and a multi-bit program control register, selected bits of which are writeable by the runtime program running on the host processor to trigger execution of a process selected from among multiple processes, the multiple processes including the FAL process and the program load process.

6. The reconfigurable processor of claim 5 , wherein the interface unit, after completion of the selected process, clears a bit of the program control register that had been set by the runtime program running on the host processor to trigger execution of the selected process.

7. The reconfigurable processor of claim 1 , the interface unit including the FAL controller, an argument load address register, an argument load size register, and a program control register; and
the FAL controller configured to recognize the FAL command in response to a write to at least one of the argument load address register, the argument load size register, or one or more argument load bits of the program control register by the runtime program running on the host processor.

8. The reconfigurable processor of claim 1 , the interface unit comprising the program load controller, a program load address register, and one or more program load bits of a program control register; and
the program load controller further configured to recognize the program load command in response to a write to at least one of the program load address register or the one or more program load bits of the program control register by the runtime program running on the host processor.

9. The reconfigurable processor of claim 8 , wherein the program load process includes:
broadcasting a program load signal to configurable units of the array of configurable units, including the configurable unit, to transition the configurable units into a state of awaiting configuration sub-files;
generating memory access requests to a memory starting at an address stored in the program load address register;

receiving the sub-files of the configuration data from the memory; and
distributing the sub-files of the configuration data to the configurable units.

10. The reconfigurable processor of claim 1 , further comprising a plurality of arrays of configurable units including the array of configurable units;
wherein the array of configurable units is a quiesceable array of configurable units configurable to implement an execution fragment of a data processing operation, configurable units in the quiesceable array further comprising quiesce logic configurable to respond to a quiesce control signal to quiesce the configurable unit on a quiesce boundary of the execution fragment; and
the quiesceable array further comprising a quiesce controller to respond to a quiesce command received from the runtime program running on the host processor by executing a quiesce process, including distributing the quiesce control signal to the configurable units in the quiesceable array, receiving respective quiesce ready signals from the configurable units, setting a quiesce ready bit of a tile status register and generating an interrupt to the host processor;
wherein the FAL controller is configurable to execute the FAL process on the quiesceable array when the quiesceable array is quiesced, remaining arrays of configurable units among the plurality of arrays of configurable units configurable to continue operations irrespective of a state of the quiesceable array.

11. The reconfigurable processor of claim 10 , wherein multiple arrays of the plurality of arrays are quiesceable.

12. The reconfigurable processor of claim 10 , wherein the runtime program is configurable to issue program load commands to each of the plurality of arrays of configurable units, use the plurality of arrays of configurable units to execute fragments of the data processing operation for a first time period, then issue quiesce commands to one or more arrays of configurable units of the plurality of arrays of configurable units, issue FAL commands to the one or more arrays of configurable units of the plurality of arrays of configurable units to update arguments therein, and execute the fragments of the data processing operation for a second time period.

13. The reconfigurable processor of claim 10 , wherein the runtime program is configurable to issue program load commands to the p

Assignees

• Sambanova Systems Inc

Inventors

• Shah Manish K
• Grohoski Gregory Frederick

Classifications

• G06F15/7867

  with reconfigurable architecture · CPC title

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F9/3013

  according to data content, e.g. floating-point registers, address registers · CPC title

• G06F15/7885 Primary

  Runtime interface, e.g. data exchange, runtime control · CPC title

• G06F9/30134

  Register stacks; shift registers · CPC title