Voltage identification signal decoder

Patent metadata

Field	Value
Publication number	US-12079054-B2
Application number	US-202217874696-A
Country	US
Kind code	B2
Filing date	Jul 27, 2022
Priority date	Jul 27, 2022
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

One example includes a VID signal decoder circuit. The circuit includes a coarse resolution decoder that receives a VID signal. The VID signal can be encoded with a digital value of an output voltage. The coarse resolution decoder can decode the VID signal to generate a first digital signal. The circuit also includes a fine resolution decoder that receives the VID signal and to decode the VID signal to generate a second digital signal. The circuit further includes a multiplexer to provide the first digital signal as an output signal responsive to a first state of a selection signal and to provide the second digital signal as the output signal responsive to a second state of the selection signal. The first and second states of the selection signal can be based on a relative amplitude of the first and second digital signals.

First claim

What is claimed is:

1. A circuit comprising:
a coarse resolution decoder configured to receive a voltage identification (VID) signal; and to decode the VID signal to generate a first digital signal;
a fine resolution decoder configured to receive the VID signal and to decode the VID signal to generate a second digital signal; and
a multiplexer coupled to the coarse resolution decoder and to the fine resolution decoder, the multiplexer configured to provide the first digital signal as an output signal responsive to a first state of a selection signal and to provide the second digital signal as the output signal responsive to a second state of the selection signal, the first and second states of the selection signal being based on a relative amplitude of the first and second digital signals.

2. The circuit of claim 1 , further comprising a resolution selector configured to monitor the first and second digital signals, to generate the selection signal at the first state responsive to a difference between the first and second digital signals being greater than a threshold, and to generate the selection signal at the second state responsive to the difference between the first and second digital signals being less than the threshold.

3. The circuit of claim 2 , wherein the threshold is a value represented by two least-significant bits between the first and second digital signals.

4. The circuit of claim 1 , wherein the VID signal is pulse-width modulated (PWM) VID signal comprising a duty-cycle representative of a digital value of an output voltage.

5. The circuit of claim 4 , wherein the coarse resolution decoder comprises:
a counter configured to determine an on-time and an off-time of each period of the PWM VID signal; and
a PWM decoder configured to implement a decoding algorithm to generate the first digital signal based on a relative difference between the on-time and the off-time of the PWM VID signal.

6. The circuit of claim 5 , wherein the decoding algorithm comprises a binary search algorithm configured to iteratively compare the duty-cycle with a target code that changes by a binary value at each most-significant bit at each iteration to decode the VID signal to generate the first digital signal.

7. The circuit of claim 4 , wherein the fine resolution decoder comprises:
an analog filter configured to filter the PWM VID signal configured to generate an analog signal representative of the duty-cycle of the PWM VID signal;
an analog-to-digital converter (ADC) configured to generate a digital representation of the analog signal representative of the duty-cycle of the PWM VID signal; and
an averaging component configured to continuously generate an average of the digital representation to decode the VID signal configured to generate the second digital signal.

8. A power controller comprising the circuit of claim 1 , the power controller being configured to receive the VID signal from a central processing unit (CPU) and to selectively activate power stages to provide respective contributions to an output voltage based on a value of the output signal to adaptively control the output voltage to the CPU.

9. An integrated circuit (IC) comprising a voltage regulator, the voltage regulator comprising the power controller of claim 8 , and further comprising the power stages.

10. A circuit comprising:
a coarse resolution decoder having a first voltage identification (VID) signal input configured to receive a VID signal and a first digital output, the coarse resolution decoder configured to provide a first digital signal at the first digital output;
a fine resolution decoder having a second VID signal input configured to receive the VID signal and a second digital output, the fine resolution decoder configured to provide a second digital signal at the second digital output;
a multiplexer having a first multiplexer input coupled to the first digital output of the coarse resolution decoder, a second multiplexer input coupled to the second digital output of the fine resolution decoder, a selection input, and a multiplexer output, the multiplexer configured to provide one of the first digital signal or the second digital signal at the multiplexer output; and
a resolution selector having a first input coupled to the first digital output of the coarse resolution decoder, a second input coupled to the second digital output of the fine resolution decoder, and a selection output coupled to the selection input of the multiplexer.

11. The circuit of claim 10 , wherein the resolution selector is configured to monitor the first and second digital signals and to generate a selection signal at the selection output at a first state responsive to a difference between the first and second digital signals being greater than a threshold, and to generate the selection signal at a second state responsive to the difference between the first and second digital signals being less than the threshold.

12. The circuit of claim 11 , wherein the threshold is a value represented by two least-significant bits between the first and second digital signals.

13. The circuit of claim 10 , wherein the VID signal input is configured to receive a pulse-width modulated (PWM) VID signal having a duty-cycle representative of a digital value of an output voltage from a central processing unit (CPU).

14. The circuit of claim 13 , wherein the coarse resolution decoder comprises:
a counter configured to determine an on-time and an off-time of periods of the PWM VID signal; and
a PWM decoder configured to implement a decoding algorithm to generate the first digital signal based on a relative difference between the on-time and the off-time of the PWM VID signal, wherein the decoding algorithm comprises a binary search algorithm configured to iteratively compare the duty-cycle with a target code that changes by a binary value at a remaining most-significant bit at each iteration to decode the VID signal to generate the first digital signal.

15. The circuit of claim 13 , wherein the fine resolution decoder comprises:
an analog filter configured to filter the PWM VID signal to generate an analog signal representative of the duty-cycle of the PWM VID signal;
an analog-to-digital converter (ADC) configured to generate a digital representation of the analog signal representative of the duty-cycle of the PWM VID signal; and
an averaging component configured to continuously generate an average of the digital representation to decode the VID signal to generate the second digital signal.

16. A circuit comprising
power stages adapted to be coupled to a central processing unit (CPU); and
a power controller configured to receive a voltage identification (VID) signal from the CPU, the VID signal being encoded with a digital value of an output voltage from the CPU, and to selectively activate the power stages based on a value of an output signal to adaptively control the output voltage to the CPU, the power controller comprising a VID decoder circuit, the VID decoder circuit comprising:
a coarse resolution decoder configured to receive the VID signal, and to decode the VID signal to generate a first digital signal;
a fine resolution decoder configured to receive the VID signal and to decode the VID signal to generate a second digital signal; and
a multiplexer configured to provide the first digital signal as the output signal responsive to a first state of a selection signal and to provide the second digital signal as the output signal responsive to a second state of the selection signal, the first and second states of the selection signal being based

Assignees

• Texas Instruments Inc

Inventors

• Shaw Vishal
• Tadeparthy Preetam
• Jain Mayank
• Anyam Karthik

Classifications

• H03M7/02

  Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word · CPC title

• H02M3/04

  by static converters · CPC title

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• H02M3/1584

  with a plurality of power processing stages connected in parallel · CPC title

• H02M1/0048

  Circuits or arrangements for reducing losses (using snubbers H02M1/34) · CPC title