Polishing pad with improved crosslinking density and process for preparing the same

Patent metadata

Field	Value
Publication number	US-12076832-B2
Application number	US-202016791881-A
Country	US
Kind code	B2
Filing date	Feb 14, 2020
Priority date	May 21, 2019
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

The present invention provides a polishing pad whose crosslinking density is adjusted to enhance the performance of the CMP process such as polishing rate and cut pad rate. In addition, in the process for preparing a polishing pad according to the embodiment, it is possible to implement such a crosslinking density by a simple method of controlling the preheating temperature of the mold for curing. Thus, the polishing pad may be applied to a process of preparing a semiconductor device, which comprises a CMP process, to provide a semiconductor device such as a wafer of excellent quality.

First claim

The invention claimed is:

1. A polishing pad, which comprises a polishing layer comprising a porous polyurethane-based resin, wherein the polishing layer has a swelling ratio of 100% to 350% in dimethylformamide (DMF) based on the volume or weight of the polishing layer, and
the polishing layer has a swelling ratio of 150% to 450% in N-methyl-2-pyrrolidone (NMP) based on the volume or weight of the polishing layer, when the polishing layer is stored in each of DMF and NMP at room temperature for 24 hours.

2. The polishing pad of claim 1 , wherein the polishing layer has a swelling ratio of 150% to 300% in DMF based on the volume of the polishing layer and a swelling ratio of 200% to 350% in DMF based on the weight of the polishing layer.

3. The polishing pad of claim 1 , wherein the polishing layer has a swelling ratio of 200% to 350% in NMP based on the volume of the polishing layer and a swelling ratio of 300% to 450% in NMP based on the weight of the polishing layer.

4. The polishing pad of claim 1 , wherein the porous polyurethane-based resin comprises a first crosslinking unit in which two urethane groups are crosslinked by a diisocyanate.

5. The polishing pad of claim 4 , wherein the first crosslinking unit comprises a structure of Formula 1:

6. The polishing pad of claim 1 , wherein the porous polyurethane-based resin comprises a second crosslinking unit in which two urea groups are crosslinked by a diisocyanate.

7. The polishing pad of claim 6 , wherein the second crosslinking unit comprises a structure of Formula 2:

8. The polishing pad of claim 1 , wherein the polishing layer has an elongation of 100% to 120% and a modulus of 30 kgf/cm 2 to 100 kgf/cm 2 .

9. The polishing pad of claim 1 , wherein the polishing layer has a polishing rate (or removal rate) of 3,000 Å/min to 4,000 Å/min against a silicon oxide layer.

10. A process for preparing a semiconductor device, which comprises polishing the surface of a semiconductor substrate using a polishing pad, wherein the polishing pad comprises a polishing layer comprising a porous polyurethane-based resin, and the polishing layer has a swelling ratio of 100% to 350% in dimethylformamide (DMF) based on the volume or weight of the polishing layer, and wherein the polishing layer has a swelling ratio of 150% to 450% in N-methyl-2-pyrrolidone (NMP) based on the volume or weight of the polishing layer, when the polishing layer is stored in each of DMF and NMP at room temperature for 24 hours.

Assignees

• Skc Solmics Co Ltd
• Sk Enpulse Co Ltd

Inventors

• Yun Jong Wook
• Joeng Eun Sun
• Heo Hye Young
• Seo Jang Won

Classifications

• H10P52/402

  of semiconductor materials · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title

• B24D11/00

  Constructional features of flexible abrasive materials; Special features in the manufacture of such materials · CPC title

• C08J9/12

  by a physical blowing agent · CPC title

• C08J2375/04

  Polyurethanes · CPC title