Reference buffer circuit, analog-to-digital converter system, receiver, base station and mobile device

Patent metadata

Field	Value
Publication number	US-12074606-B2
Application number	US-202017131811-A
Country	US
Kind code	B2
Filing date	Dec 23, 2020
Priority date	Dec 23, 2020
Publication date	Aug 27, 2024
Grant date	Aug 27, 2024

Abstract

A reference buffer circuit for an analog-to-digital converter is provided. The reference buffer circuit includes a first input node configured to receive a first bias signal of a first polarity from a first signal line. Further, the reference buffer circuit includes a second input node configured to receive a second bias signal of a second polarity from a second signal line. Additionally, the reference buffer circuit includes a first output node configured to output a first reference signal of the first polarity. A first buffer amplifier is coupled between the first input node and the first output node. The reference buffer circuit includes in addition a second output node configured to output a second reference signal of the second polarity. A second buffer amplifier is coupled between the second input node and the second output node. Further, the reference buffer circuit includes a first coupling path comprising a first capacitive element. The first coupling path is coupled between the first output node and the second input node. In addition, the reference buffer circuit includes a second coupling path comprising a second capacitive element. The second coupling path is coupled between the second output node and the first input node.

First claim

What is claimed is:

1. A reference buffer circuit for an analog-to-digital converter, the reference buffer circuit comprising:
a first input node configured to receive a first bias signal of a first polarity from a first signal line;
a second input node configured to receive a second bias signal of a second polarity from a second signal line;
a first output node configured to output a first reference signal of the first polarity, wherein a first buffer amplifier is coupled between the first input node and the first output node;
a second output node configured to output a second reference signal of the second polarity, wherein a second buffer amplifier is coupled between the second input node and the second output node;
a first coupling path comprising a first capacitive element, wherein the first coupling path is coupled between the first output node and the second input node; and
a second coupling path comprising a second capacitive element, wherein the second coupling path is coupled between the second output node and the first input node; and
a third coupling path comprising a third capacitive element coupled between the first input node and the second input node.

2. The reference buffer circuit of claim 1 , wherein a capacitance of the first capacitive element is equal to a capacitance of the second capacitive element.

3. The reference buffer circuit of claim 1 , wherein a respective capacitance of at least one of the first capacitive element and the second capacitive element is at minimum 50% and at maximum 150% of a gate-source capacitance of any transistor of the first buffer amplifier.

4. The reference buffer circuit of claim 1 , wherein the first coupling path additionally comprises at least one of first resistive element and a first inductive element, and wherein the second coupling path additionally comprises at least one of second resistive element and a second inductive element.

5. The reference buffer circuit of claim 1 , wherein a capacitance of the third capacitive element is equal to or greater than a gate-source capacitance of any transistor of the first buffer amplifier.

6. The reference buffer circuit of claim 1 , further comprising a fourth capacitive element coupled between the first input node and a ground node.

7. The reference buffer circuit of claim 6 , wherein a capacitance of the fourth capacitive element is equal to or greater than a gate-source capacitance of any transistor of the first buffer amplifier.

8. The reference buffer circuit of claim 1 , further comprising a fifth capacitive element coupled between the second input node and a ground node.

9. The reference buffer circuit of claim 8 , wherein a capacitance of the fifth capacitive element is equal to or greater than a gate-source capacitance of any transistor of the first buffer amplifier.

10. The reference buffer circuit of claim 1 , wherein at least one the first buffer amplifier and the second buffer amplifier is a source follower circuit.

11. The reference buffer circuit of claim 1 , wherein at least one the first buffer amplifier and the second buffer amplifier comprises cascaded source follower circuits.

12. An analog-to-digital converter, ADC, system, comprising:
a biasing circuit configured to supply a first bias signal of a first polarity to a first signal line and a second bias signal of a second polarity to a second signal line;
a plurality of sub-ADCs for digitizing an analog input signal, wherein the plurality of sub-ADCs are coupled to the first signal line and the second signal line for receiving the first bias signal and the second bias signal, and wherein at least one of the plurality of sub-ADCs comprises a reference buffer circuit according to claim 1 for coupling the at least one of the plurality of sub-ADCs to the first signal line and the second signal line.

13. The ADC system of claim 12 , wherein the at least one of the plurality of sub-ADCs further comprises:
a first plurality of switches for selectively coupling a first plurality of loads to the first output node of the respective reference buffer; and
a second plurality of switches for selectively coupling a second plurality of loads to the second output node of the respective reference buffer.

14. The ADC system of claim 12 , wherein the plurality of sub-ADCs are time-interleaved.

15. The ADC system of claim 12 , wherein the plurality of sub-ADCs are pipelined.

16. A receiver, comprising:
an analog-to-digital converter system according to claim 12 ; and
analog circuitry configured to receive a receive signal, and to supply the analog input signal to the analog-to-digital converter system based on the receive signal.

17. The receiver of claim 16 , wherein the receive signal is a radio frequency receive signal from an antenna element.

18. The receiver of claim 16 , wherein the analog circuitry is configured to receive the receive signal from a wired transmission link.

19. A base station, comprising:
a receiver according to claim 16 ; and
a transmitter configured to generate a radio frequency transmit signal.

20. The base station of claim 19 , further comprising at least one antenna element coupled to at least one of the receiver and the transmitter.

Assignees

• Intel Corp

Inventors

• Gruber Daniel
• Lindholm Christian
• Clara Martin
• Cascio Giacomo

Classifications

• H04B1/12

  Neutralising, balancing, or compensation arrangements · CPC title

• H03K19/018578

  with at least one differential stage · CPC title

• H03K19/00384

  in field effect transistor circuits · CPC title

• H03F3/30

  Single-ended push-pull {[SEPP]} amplifiers {(single-ended sense amplifiers G11C7/067)}; Phase-splitters therefor · CPC title

• H03M1/1215

  using time-division multiplexing · CPC title