Light emitting diode chip and method for manufacturing the same, display device

Patent metadata

Field	Value
Publication number	US-12074258-B2
Application number	US-202117332852-A
Country	US
Kind code	B2
Filing date	May 27, 2021
Priority date	Oct 14, 2020
Publication date	Aug 27, 2024
Grant date	Aug 27, 2024

Abstract

An embodiment of the present disclosure provides a light emitting diode chip, including: a light emitting functional layer including a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked, and a second semiconductor layer including a plurality of second semiconductor patterns which are arranged at intervals; a first electrode layer including a first electrode pattern electrically coupled to the first semiconductor layer; a second electrode layer disposed on a side, away from the light emitting layer, of the second semiconductor layer and including a plurality of second electrode patterns in one-to-one correspondence with the second semiconductor patterns, and the second electrode patterns are electrically coupled to the second semiconductor patterns correspondingly. Embodiments of the present disclosure further provide a method for manufacturing a light emitting diode chip and a display device.

First claim

The invention claimed is:

1. A display device, comprising a light emitting diode chip, wherein the light emitting diode chip comprises:
a light emitting functional layer comprising a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked, and the second semiconductor layer comprises a plurality of second semiconductor patterns which are arranged at intervals;
a first electrode layer comprising a first electrode pattern electrically coupled to the first semiconductor layer; and
a second electrode layer disposed on a side, away from the light emitting layer, of the second semiconductor layer and comprising a plurality of second electrode patterns in one-to-one correspondence with the second semiconductor patterns, and the second electrode patterns are electrically coupled to the second semiconductor patterns correspondingly,
wherein the first electrode pattern is disposed on a side surface of the first semiconductor layer, so that an orthographic projection of the first electrode pattern on a plane in which the first semiconductor layer is located is at least partially not overlapped with the first semiconductor layer,
the display device further comprises: a driving substrate;
the driving substrate comprises a driving functional layer and a pixel defining layer, wherein the driving functional layer comprises a plurality of first coupling terminals, the pixel defining layer defines a plurality of pixel accommodating holes, and each of the pixel accommodating holes corresponds to more than one light emitting diode chips,
more than one of the first coupling terminals are disposed in each of the pixel accommodating holes, and each of the light emitting diode chips is flip-mounted in a corresponding one of the pixel accommodating holes, and the second electrode patterns are electrically coupled to the first coupling terminals in the corresponding one of the pixel accommodating holes,
wherein at least a part of the first electrode pattern protrudes from a side of the pixel accommodating hole away from the driving functional layer,
for the light emitting diode chips corresponding to any one pixel accommodating hole, first electrode patterns of adjacent ones of the light emitting diode chips are in contact with each other,
the pixel accommodating hole is configured with at least one second coupling terminal disposed on a side of the pixel defining layer away from the driving functional layer, the second coupling terminal being electrically coupled to a corresponding signal line in the driving functional layer, and
for the light emitting diode chips corresponding to any one pixel accommodating hole, the first electrode pattern of at least one light emitting diode chip disposed on an outermost side is electrically coupled to the second coupling terminal corresponding to the pixel accommodating hole.

2. The display device of claim 1 , wherein the first electrode pattern is in contact with the side surface of the first semiconductor layer.

3. The display device of claim 1 , wherein the light emitting diode chip further comprises an insulating layer, the insulating layer is disposed on a side, away from the light emitting layer, of the second semiconductor layer, and a plurality of via holes corresponding to the second semiconductor patterns are formed in the insulating layer;
the second electrode layer is disposed on a side, away from the second semiconductor layer, of the insulating layer, and the second electrode patterns are electrically coupled to the second semiconductor patterns correspondingly through the via holes.

4. The display device of claim 1 , wherein the light emitting diode chip further comprises a transparent electrode disposed between the second electrode pattern and the corresponding second semiconductor pattern.

5. The display device of claim 1 , wherein an orthographic projection of the light emitting layer on a plane where the first semiconductor layer is located is within an area where the first semiconductor layer is located, and the orthographic projection of the light emitting layer on the plane where the first semiconductor layer is located covers a partial area of the first semiconductor layer.

6. The display device of claim 1 , wherein the light emitting diode chip further comprises a buffer layer disposed on a side, away from the light emitting layer, of the first semiconductor layer.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhang Lizhen
• Yuan Guangcai
• Yao Qi
• Wang Mingxing

Classifications

• H10W90/00

  Package configurations · CPC title

• H10H20/032

  of electrodes · CPC title

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10H20/815

  having stress relaxation structures, e.g. buffer layers · CPC title