Memory system and operating method of the memory system

Patent metadata

Field	Value
Publication number	US-12073896-B2
Application number	US-202217890784-A
Country	US
Kind code	B2
Filing date	Aug 18, 2022
Priority date	Mar 23, 2022
Publication date	Aug 27, 2024
Grant date	Aug 27, 2024

Abstract

A memory system and a method of operating the memory system are provided. The memory system includes a plurality of semiconductor memory devices each of which includes a plurality of memory blocks. The memory system also includes a controller configured to control the plurality of semiconductor memory devices to perform a program operation, a read operation, and an operation of removing a hole in a space region on a target memory block of the plurality of memory blocks. The controller controls the plurality of semiconductor memory devices to perform the operation of removing the hole in the space region on the target memory block when an erase count of the target memory block of the plurality of memory blocks is greater than a set value.

First claim

What is claimed is:

1. A memory system, comprising:
a plurality of semiconductor memory devices each of which includes a plurality of memory blocks; and
a controller configured to control the plurality of semiconductor memory devices to perform a program operation, a read operation, and an operation of removing a hole in a space region on a target memory block of the plurality of memory blocks,
wherein the controller controls the plurality of semiconductor memory devices to perform the operation of removing the hole in the space region on the target memory block when an erase count of the target memory block is greater than a set value.

2. The memory system of claim 1 , wherein the controller includes an erase counter that counts and manages the erase count of each of the plurality of memory blocks.

3. The memory system of claim 1 , wherein the plurality of semiconductor memory devices apply a set voltage to all word lines of the target memory block for which the erase count is greater than the set value during the operation of removing the hole in the space region.

4. The memory system of claim 3 , wherein the plurality of semiconductor memory devices apply a ground voltage to bit lines or a source line of the target memory block during the operation of removing the hole in the space region.

5. The memory system of claim 3 , wherein the plurality of semiconductor memory devices turn on source select transistors or drain select transistors included in the target memory block during the operation of removing the hole in the space region.

6. The memory system of claim 3 , wherein the set voltage has a same potential level as a program voltage used to perform the program operation.

7. A memory system, comprising:
a memory device including a plurality of memory blocks; and
a controller configured to control the memory device to perform a program operation, a read operation, and an operation of removing a hole in a space region on the plurality of memory blocks,
wherein the controller includes an erase counter for counting an erase count of each of the plurality of memory blocks and controls the memory device to perform the operation of removing the hole in the space region on a target memory block for which the erase count counted by the erase counter is greater than a set value.

8. The memory system of claim 7 , wherein the memory device applies a set voltage to all word lines of the target memory block during the operation of removing the hole in the space region.

9. The memory system of claim 8 , wherein the set voltage has a same potential level as a program voltage used to perform the program operation.

10. The memory system of claim 8 , wherein the memory device applies a ground voltage to bit lines or a source line of the target memory block during the operation of removing the hole in the space region.

11. The memory system of claim 8 , wherein the memory device turns on source select transistors or drain select transistors included in the target memory block during the operation of removing the hole in the space region.

12. A method of operating a memory system, the method comprising:
counting an erase count for each memory block of a plurality of memory blocks;
designating, as a target memory block, a memory block among the plurality of memory blocks for which the counted erase count is greater than a set value; and
performing an operation of removing a hole in a space region on the target memory block.

13. The method of claim 12 , wherein performing the operation of removing the hole in the space region comprises applying a set voltage to all word lines of the target memory block.

14. The method of claim 13 , wherein the set voltage has a same potential level as a program voltage that is applied to a selected word line during a program operation.

15. The method of claim 13 , wherein performing the operation of removing the hole in the space region comprises applying a ground voltage to bit lines or a source line of the target memory block.

16. The method of claim 13 , wherein performing the operation of removing the hole in the space region comprises turning on source select transistors or drain select transistors included in the target memory block.

Assignees

• Sk Hynix Inc

Inventors

• Choi Gil Bok
• Seo Moon Sik
• Yun dae hwan

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title