Display panel

Patent metadata

Field	Value
Publication number	US-12073787-B2
Application number	US-202318320042-A
Country	US
Kind code	B2
Filing date	May 18, 2023
Priority date	May 29, 2020
Publication date	Aug 27, 2024
Grant date	Aug 27, 2024

Abstract

A display panel includes pixel circuits, and the pixel circuit includes: a driving sub-circuit, a fourth sub-circuit and a first reset sub-circuit. The driving sub-circuit includes a driving transistor and a storage capacitor. The driving transistor includes a gate and an active pattern including a source portion and a drain portion. The storage capacitor includes a first storage electrode sharing a same electrode with the gate and a second storage electrode used to be connected to a first voltage signal line. The fourth sub-circuit is configured such that the drain portion and the gate are connected when being turned on. The first reset sub-circuit includes a first active pattern, which is arranged in a same layer as the active pattern and includes a first source portion being used to be connected to a first initialization signal line and a first drain portion being connected to the drain portion.

First claim

What is claimed is:

1. A display panel, comprising:
a plurality of pixel circuits, wherein a pixel circuit in the plurality of pixel circuits includes:
a driving sub-circuit, wherein the driving sub-circuit includes:
a driving transistor, wherein the driving transistor includes a gate and an active pattern, the active pattern includes a source portion and a drain portion; and
a storage capacitor, wherein the storage capacitor includes a first storage electrode and a second storage electrode, the first storage electrode and the gate share a same electrode, and the second storage electrode is used to be connected to a first voltage signal line;

a fourth sub-circuit, wherein the fourth sub-circuit is configured such that the drain portion and the gate are connected when the fourth sub-circuit is turned on; and
a first reset sub-circuit, wherein the first reset sub-circuit includes a first active pattern; the first active pattern is arranged in a same layer as the active pattern, and the first active pattern includes a first source portion and a first drain portion; the first drain portion is connected to the drain portion, and the first source portion is used to be connected to a first initialization signal line.

2. The display panel according to claim 1 , wherein the fourth sub-circuit includes a sixth transistor, the sixth transistor includes a sixth active pattern, and a material of the sixth active pattern includes an oxide semiconductor material.

3. The display panel according to claim 2 , wherein the pixel circuit further includes a third sub-circuit, and the third sub-circuit includes a fifth transistor; the fifth transistor includes a fifth active pattern, and the fifth active pattern includes a fifth source portion and a fifth drain portion; the fifth drain portion and the source portion are connected to be a one-piece structure, and the fifth source portion is used to be connected to a data line; and
the fifth transistor further includes a fifth gate, and the sixth transistor further includes a sixth gate, wherein
portions of two different scanning lines serve as the fifth gate and the sixth gate, respectively, and one of the two different scanning lines, a portion of which serves as the fifth gate, is arranged in the same layer as the gate, and another of the two different scanning lines, a portion of which serves as the sixth gate, is located in a different layer from the gate; or

the fifth transistor further includes the fifth gate, and the sixth transistor further includes a sixth bottom gate and a sixth top gate, wherein
portions of two scanning lines serve as the sixth bottom gate and the sixth top gate, respectively, and the two scanning lines are located in different layers; a portion of another scanning line serves as the fifth gate, and the another scanning line is arranged in the same layer as the gate and in a different layer from the two scanning lines.

4. The display panel according to claim 2 , wherein the display panel further comprises a first connection layer, wherein
the first connection layer includes a first connection electrode; the sixth active pattern includes a sixth source portion and a sixth drain portion; the sixth drain portion is electrically connected to the gate through the first connection electrode, and the sixth source portion is electrically connected to the drain portion; and
the first connection electrode, the gate and the second storage electrode are located in different layers.

5. The display panel according to claim 4 , wherein the second storage electrode is located between the gate and the first connection electrode in a thickness direction of the display panel;
the second storage electrode includes an opening, and the opening overlaps with a portion, connected to the gate in the thickness direction of the display panel, of the first connection electrode.

6. The display panel according to claim 1 , wherein the display panel further comprises a first connection layer, wherein
the first connection layer includes a second connection electrode; the first drain portion and the drain portion are electrically connected through the second connection electrode; and
the second connection electrode, the gate and the second storage electrode are located in different layers.

7. The display panel according to claim 6 , wherein the first initialization signal line is located in the first connection layer;
the first transistor further includes a first gate; a portion of a first reset signal line serves as the first gate, and the first reset signal line is arranged in a same layer as the gate;
extending directions of the first reset signal line and the first initialization signal line are approximately same.

8. The display panel according to claim 6 , wherein the pixel circuit further includes a second sub-circuit, and the second sub-circuit includes a fourth transistor;
the fourth transistor includes a fourth active pattern, and the fourth active pattern includes a fourth source portion and a fourth drain portion; the fourth source portion and the drain portion are connected to be a one-piece structure, and the fourth drain portion is used to be connected to a light-emitting device.

9. The display panel according to claim 8 , wherein the pixel circuit further includes a first sub-circuit, and the first sub-circuit includes a third transistor; the third transistor includes a third active pattern, and the third active pattern includes a third source portion and a third drain portion; the third drain portion and the source portion are connected to be a one-piece structure;
the first connection layer further includes a third connection electrode, and the third source portion and the second storage electrode are electrically connected through the third connection electrode.

10. The display panel according to claim 9 , wherein the display panel further comprises a second connection layer, and the first voltage signal line and the data line are located in the second connection layer;
the fourth sub-circuit includes a sixth transistor, and the sixth transistor includes a sixth active pattern; the sixth active pattern is located in a different layer from both the active pattern and the fifth active pattern, and a material of the sixth active pattern includes an oxide semiconductor material;
the first connection layer further includes a first connection electrode; the sixth active pattern includes a sixth source portion and a sixth drain portion; the sixth drain portion is electrically connected to the gate through the first connection electrode, and the sixth source portion is electrically connected to the drain portion; and
a layer where the gate is located, a layer where the second storage electrode is located, the first connection layer and the second connection layer are sequentially arranged along a thickness direction of the display panel; the first voltage signal line covers the first connection electrode in the thickness direction of the display panel.

11. The display panel according to claim 9 , wherein the fourth transistor further includes a fourth gate, and the third transistor further includes a third gate;
two portions of a same enable signal line serve as the third gate and the fourth gate, respectively, and the enable signal line is arranged in a same layer as the gate; or two portions of two different enable signal lines serve as the third gate and the fourth gate, respectively.

12. The pixel circuit according to claim 9 , further comprising:
a plurality of light-emitting devices, the light-emitting device being one of the plurality of light-emitting devices, wherein
the pixel circuit further includes a s

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Wang Rui
• Qiu Haijun
• Shang Fei
• Hu Ming
• Li Shaoru
• Ko Minho

Classifications

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title