System and method for the detection of processing hot-spots

Patent metadata

Field	Value
Publication number	US-12073218-B2
Application number	US-202117194527-A
Country	US
Kind code	B2
Filing date	Mar 8, 2021
Priority date	Mar 8, 2021
Publication date	Aug 27, 2024
Grant date	Aug 27, 2024

Abstract

A system and method for the storage, within one or more virtual execution context registers, tracing information indicative of process/code flow within a processor system. This stored information can include a time stamp, information indicative of where the instruction pointer of the system was pointing prior to any process discontinuity, information indicative of where the instruction pointer of the system was pointing after any process discontinuity, and the number of times a specific instruction or sub-process is executed during a particular process. The data collected and stored can be utilized within such a system for the identification and analysis of processing hot-spots.

First claim

The invention claimed is:

1. A system for recognizing processing hot-spots comprising:
at least one processor coupled with a memory;
the memory including:
a plurality of addressable virtual registers, wherein each of the addressable virtual registers stores code indicative of an individual process step;
a plurality of code execution registers, each dedicated to storing information related to a particular individual process step; and
the at least one processor adapted to:
execute at least one process comprising sequentially executing one or more identifiable process steps as indicated by the code stored within the plurality of addressable virtual registers,
record a number of times, within the execution of the at least one process, a particular identifiable process step, as indicated by the code stored within the plurality of addressable virtual registers, is executed, wherein the number of times the particular identifiable process step is executed is determined based on a number of times a specific identifiable code location for the particular identifiable process step occurs within the execution of the at least on process;
store a value indicative of the number of times a particular identifiable process step is executed in a particular one of the plurality of code execution registers dedicated to the particular identifiable process step; and
classify a particular identifiable process step as a process hot-spot based, at least in part, upon the stored value indicative of the number of times a particular identifiable process step is executed and the stored value is a highest count value among the plurality of code execution registers.

2. The system of claim 1 wherein recording the number of times, within the execution of the at least one process, a particular identifiable process step, as indicated by the code stored within the plurality of addressable virtual registers, is executed comprises increasing a monotonic counter.

3. The system of claim 1 wherein the plurality of code execution registers comprises at least one of the following:
a virtual memory; and
a physical memory.

4. The system of claim 1 wherein the at least one processor comprises at least one of the following:
a physical processor; and
a virtual processor.

5. The system of claim 1 wherein the plurality of addressable virtual registers comprises a virtual context memory.

6. The system of claim 5 wherein the virtual execution context memory comprises at least one of the following:
static random-access memory;
dynamic random-access memory;
a non-volatile memory; and
a three-dimensional cross-point memory.

7. A method for recognizing processing hot-spots: in a system comprising:
a plurality of addressable virtual registers, wherein each of the addressable virtual registers stores code indicative of an individual process step;
a plurality of code execution registers, each dedicated to storing information related to a particular individual process step; and
at least one processor adapted to:
execute at least one process comprising sequentially executing one or more identifiable process steps as indicated by the code stored within the plurality of addressable virtual registers;
the method comprising the steps of:
recording a number of times, within the execution of the at least one process, a particular identifiable process step, as indicated by the code stored within the plurality of addressable virtual registers, is executed, wherein the number of times the particular identifiable process step is executed is determined based on a number of times a specific identifiable code location for the particular identifiable process step occurs within the execution of the at least on process;
storing a value indicative of the number of times a particular identifiable process step is executed m a particular one of the plurality of code execution registers dedicated to the particular identifiable process step; and
classifying a particular identifiable process step as a process hot-spot based, at least in part, upon the stored value indicative of the number of times a particular identifiable process step is executed and the stored value is a highest count value among the plurality of code execution registers.

8. The method of claim 7 wherein the step of recording comprises increasing a monotonic counter.

9. The method of claim 7 wherein the plurality of code execution registers comprises at least one of the following:
a virtual memory; and
a physical memory.

10. The method of claim 7 wherein the at least one processor comprises at least one of the following:
a physical processor; and
a virtual processor.

11. The method of claim 7 wherein the plurality of addressable virtual registers comprises a virtual context memory.

12. The method of claim 11 wherein the virtual execution context memory comprises at least one of the following:
static random-access memory;
dynamic random-access memory:
a non-volatile memory; and
a three-dimensional cross-point memory.

Assignees

• Beale Andrew Ward
• Strong David
• Unisys Corp

Inventors

• Beale Andrew Ward
• Strong David

Classifications

• G06F11/3442

  for planning or managing the needed capacity · CPC title

• G06F12/0623

  for memory modules · CPC title

• G06F2212/452

  Instruction code · CPC title

• G06F9/30127

  Register windows · CPC title

• G06F12/109

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title