Detector circuit for start signaling in an eUSB repeater

Patent metadata

Field	Value
Publication number	US-12072825-B2
Application number	US-202218073498-A
Country	US
Kind code	B2
Filing date	Dec 1, 2022
Priority date	Dec 1, 2022
Publication date	Aug 27, 2024
Grant date	Aug 27, 2024

Abstract

A detector circuit is described for start signaling in an eUSB repeater. In an example, a circuit includes an analog differential transceiver configured to receive a differential data signal from a differential data bus and configured to drive a differential data signal to the differential data bus, an analog single-ended transceiver configured to receive a single-ended data signal from a single-ended data bus and configured to drive a single-ended data signal to the single-ended data bus, repeater logic coupled to the analog differential transceiver and the analog single-ended transceiver to repeat data signals between the differential data bus and the single-ended data bus, the repeater logic having an active state and a low power state, and a detection circuit coupled to the analog single-ended transceiver to detect a start signal on the single-ended data bus and to generate a wake signal to the repeater logic upon detecting the start signal.

First claim

What is claimed is:

1. An embedded USB (eUSB) repeater having:
an analog differential transceiver configured to receive a differential data signal from a differential data bus and configured to drive a differential data signal to the differential data bus;
an analog single-ended transceiver configured to receive a single-ended data signal from a single-ended data bus and configured to drive a single-ended data signal to the single-ended data bus;
repeater logic coupled to the analog differential transceiver and the analog single-ended transceiver to repeat data signals between the differential data bus and the single-ended data bus,
the repeater logic having an active state and a low power state; and
a detection circuit coupled to the analog single-ended transceiver and configured to detect a start signal on the single-ended data bus;
wherein the detection circuit includes,
a clock;
a first state element coupled to detect and store the start signal on a rising edge of the clock; and
a second state element coupled to capture, on a falling edge of the clock, the start signal stored in the first state element; and

wherein the detection circuit is configured to generate and send a wake signal to the repeater logic in response to at least one of the first state element detecting the start signal on the rising edge of the clock, and the second state element capturing the start signal on the falling edge of the clock.

2. The repeater of claim 1 ,
wherein the repeater logic is in the low power state upon receiving the wake signal.

3. The repeater of claim 1 ,
wherein the detection circuit has a suspend mode and
wherein the repeater logic sends a reset signal to the detection circuit to place the detection circuit in the suspend mode when the repeater logic is in the active state.

4. The repeater of claim 1 ,
wherein the repeater logic comprises high level logic,
wherein the start signal comprises a start of control message, and
wherein the detection circuit is configured to send the start of control message to the high level logic.

5. The repeater of claim 1 ,
wherein the repeater is a device side eUSB repeater and the start signal comprises a start of wake signal.

6. The repeater of claim 1 ,
wherein the repeater is a host side eUSB repeater and the start signal comprises a start of resume signal.

7. The repeater of claim 1 ,
wherein the repeater logic has a first clock and the detection circuit has a second clock slower than the first clock.

8. The repeater of claim 1 , wherein the detection circuit includes:
a positive section configured to detect the start signal on the rising edge of the clock and generate a first wake signal;
a negative section configured to detect the start signal on the falling edge of the clock and generate a second wake signal; and
a gate coupled to both the positive section and the negative section and configured to pass the first wake signal and the first wake signal in response to the positive section and the negative section detecting the start signal.

9. The repeater of claim 1 :
wherein the first state element is a first sync flop having a clock input coupled to the clock and
wherein the second state element is a second sync flop also having a clock input coupled to the clock.

10. The repeater of claim 1 , further comprising
a counter coupled to the second state element to receive the start signal transition and to determine a duration of the start signal after the start signal transition and before a next start signal transition.

11. The repeater of claim 10 ,
wherein the counter generates a start of control message if the determined duration of the start signal reaches a predetermined counter value.

12. The repeater of claim 1 ,
wherein the low power state includes an eUSB L2 state.

13. A host embedded USB (eUSB) repeater comprising:
an analog differential transceiver configured to receive a USB signal from a USB bus coupled to a remote device and configured to drive a USB signal to the remote device on the USB bus;
an analog single-ended transceiver configured to receive an eUSB signal from an eUSB bus coupled to a host and configured to drive an eUSB signal to the host on the eUSB bus;
repeater logic coupled to the analog differential transceiver and the analog single-ended transceiver to repeat data signals between the USB bus and the eUSB bus,
the repeater logic having an active state and a low power state; and
a detection circuit coupled to the analog single-ended transceiver to detect a start of resume (SOR) from the host on the eUSB bus;
wherein the detection circuit includes,
a clock;
a first sync flop coupled to detect and store the SOR on a rising edge of the clock; and
a second sync flop coupled to capture, on a falling edge of the clock, the SOR stored in the first sync flop; and

wherein the detection circuit is configured to generate and send a resume signal to the repeater logic in response to at least one of the first sync flop detecting the SOR on the rising edge of the clock, and the second sync flop capturing the SOR on the falling edge of the clock.

14. The repeater of claim 13 ,
wherein the SOR starts with both lines of the eUSB bus being driven high followed by one line going low for several milliseconds.

15. The repeater of claim 14 ,
wherein the detection circuit comprises an AND gate to compare a current detected SOR to a previous stored state of the eUSB bus to detect an SOR.

16. An embedded USB (eUSB) repeater having:
an analog differential transceiver configured to receive a differential data signal from a differential data bus and configured to drive a differential data signal to the differential data bus;
an analog single-ended transceiver configured to receive a single-ended data signal from a single-ended data bus and configured to drive a single-ended data signal to the single-ended data bus;
repeater logic coupled to the analog differential transceiver and the analog single-ended transceiver to repeat data signals between the differential data bus and the single-ended data bus,
the repeater logic having an active state and a low power state; and
a detection circuit coupled to the analog single-ended transceiver and configured to detect a start signal on the single-ended data bus;
wherein the detection circuit includes,
a clock;
a positive section including,
a first state element coupled to detect and store the start signal on a rising edge of the clock; and
a second state element coupled to capture, on a falling edge of the clock, the start signal stored in the first state element; and

a negative section including,
a third state element coupled to detect and store the start signal on the falling edge of the clock; and
a fourth state element coupled to capture, on the rising edge of the clock, the start signal stored in the first state element; and

wherein the detection circuit is configured to generate and send a wake signal to the repeater logic in response to at least one of the first state element detecting the start signal on the rising edge of the clock, the second state element capturing the start signal on the falling edge of the clock, the third state element detecting the start signal on the falling edge of the clock, and the fourth state element capturing the start signal on the rising edge of the clock.

Assignees

• Nxp Usa Inc

Inventors

• Jaramillo Kenneth

Classifications

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• G06F13/4004 Primary

  Coupling between buses · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F13/4045 Primary

  where the bus bridge performs an extender function · CPC title