Method for manufacturing a magnetic random-access memory device using post pillar formation annealing

Patent metadata

Field	Value
Publication number	US-12069957-B2
Application number	US-202217721369-A
Country	US
Kind code	B2
Filing date	Apr 15, 2022
Priority date	Jan 28, 2019
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both anneal the memory element pillars to form a desired grain structure in the memory element pillars and also to perform back end of line thermal processing for circuitry associated with the memory element array.

First claim

What is claimed is:

1. A method for manufacturing a magnetic data recording device, the method comprising:
forming circuitry on a wafer;
forming an array of magnetic memory element pillars on the wafer, and forming a dielectric isolation material surrounding the array of magnetic memory element pillars, wherein the circuitry is associated with the array of magnetic memory element pillars formed on the wafer; and
after forming the array of magnetic memory element pillars, the dielectric isolation material and the circuitry on the wafer, performing a thermal annealing process that is configured to simultaneously anneal the magnetic memory element pillars and also perform a back end of line thermal processing of the circuitry,
wherein the thermal annealing process comprises a rapid thermal annealing process that comprises heating the wafer to a temperature of about 400° C. and cooling the wafer to room temperature in less than 60 seconds in a vacuum of about 1×10 −4 Torr;
wherein the magnetic memory element pillars each include a MgO barrier layer, and wherein the thermal annealing process is configured to form a desired grain structure in the MgO barrier layer.

2. The method of claim 1 , wherein each magnetic memory element pillar comprises a magnetic reference layer, a magnetic free layer, a thin, non-magnetic, electrically insulating barrier layer located between the magnetic reference layer and the magnetic free layer, and a spin polarization layer over the magnetic free layer.

3. The method of claim 1 , wherein the array of magnetic memory element pillars comprise a few thousands of magnetic memory element pillars.

4. The method of claim 1 , wherein the circuitry is a COMS circuitry that comprises a semiconductor material formed over a doped portion of the wafer, a gate dielectric, and a gate lead structure.

5. The method of claim 1 , further comprising:
forming a conductive lead between the array of magnetic memory element pillars and the circuitry.

6. The method of claim 1 , wherein the dielectric isolation material comprises one or more layers of silicon oxide and silicon nitride.

7. The method of claim 1 , wherein the dielectric isolation material is deposited through a Plasma Vapor Deposition (PVD) sputter deposition, atomic layer deposition (ALD), or chemical vapor deposition (CVD).

8. The method of claim 1 , further comprising:
forming a top lead over the dielectric isolation material, the top lead contacting the array of magnetic memory element pillars.

9. The method of claim 8 , wherein no thermal annealing process is employed before forming the top lead over the dielectric isolation material.

10. The method as in claim 1 , wherein the magnetic memory element pillars each include a non-magnetic barrier layer, and wherein the thermal annealing process is configured to form a desired grain structure in the non-magnetic barrier layer.

11. The method as in claim 1 , each of the magnetic memory element pillars comprises a non-magnetic barrier layer comprising MgO and a cap layer comprising MgO, and wherein the barrier layer and cap layer are configured to define a ratio of barrier layer area resistance to cap layer area resistance that allows for desired performance parameters of the magnetic memory element pillar.

12. A method for manufacturing a magnetic data recording device, the method comprising:
forming circuitry on a wafer;
forming an array of magnetic memory element pillars on the wafer, and forming a dielectric isolation material surrounding the array of magnetic memory element pillars, wherein the circuitry is associated with the array of magnetic memory element pillars formed on the wafer;
forming a top lead over the array of magnetic memory element pillars and the dielectric isolation material, the top lead contacting the array of magnetic memory element pillars; and
performing a thermal annealing process that is configured to simultaneously anneal the magnetic memory element pillars and also perform a back end of line thermal processing of the circuitry,
wherein the thermal annealing process comprises heating the wafer to a temperature of about 400° C. for a duration of about 60 minutes in a vacuum and cooling the wafer to room temperature in a first cooling step in a vacuum and in a second cooling step in an N2 atmosphere; and
wherein the magnetic memory element pillars each include a MgO barrier layer, and wherein the thermal annealing process is configured to form a desired grain structure in the MgO barrier layer.

13. The method of claim 12 , wherein each magnetic memory element comprises a magnetic reference layer, a magnetic free layer, a thin, non-magnetic, electrically insulating barrier layer located between the magnetic reference layer and the magnetic free layer, and a spin polarization layer over the magnetic free layer.

14. The method of claim 12 , wherein the circuitry is a COMS circuitry that comprises a semiconductor material formed over a doped portion of the wafer, a gate dielectric, and a gate lead structure.

15. The method of claim 12 , wherein the thermal annealing process comprises:
heating the wafer to a temperature of 350-450 degrees C. and maintaining that temperature for a duration of 40-100 minutes in a vacuum;
cooling the wafer to a temperature of 100-140 degrees C. in a vacuum; and
cooling the wafer to a temperature of 30-50 degrees C. in an N 2 atmosphere.

16. The method as in claim 12 , wherein the thermal annealing process comprises:
heating the wafer to a temperature of 350-450 degrees C. and maintaining that temperature for a duration of 40-100 minutes in a vacuum of at least 10 −4 Torr;
cooling the wafer to a temperature of 100-140 degrees C. in a vacuum of at least 10 −4 Torr; and
cooling the wafer to a temperature of 30-50 degrees C. in an N 2 atmosphere.

17. The method as in claim 13 , wherein the thermal annealing process is configured to form a desired grain structure in the non-magnetic barrier layer.

Assignees

• Integrated Silicon Solution Cayman Inc

Inventors

• Vasquez Jorge
• KARDASZ Bartlomiej Adam
• Hernandez Jacob Anthony
• Boone Thomas D
• Wolf Georg
• Pinarbasi Mustafa

Classifications

• H10N50/85

  Materials of the active region · CPC title

• H10B61/00

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10N50/80

  Constructional details · CPC title

• H01F10/3254

  the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ] · CPC title

• H01F10/3286

  Spin-exchange coupled multilayers having at least one layer with perpendicular magnetic anisotropy · CPC title