Thin film anisotropic magnetoresistor device and formation

Patent metadata

Field	Value
Publication number	US-12069956-B2
Application number	US-202117487877-A
Country	US
Kind code	B2
Filing date	Sep 28, 2021
Priority date	Sep 28, 2021
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

Apparatus, and their methods of manufacture, including an integrated circuit device having metallization layers for interconnecting underlying electronic devices. Contacts contact conductors of an uppermost one of the metallization layers. A planarized first dielectric layer covers the contacts and the uppermost one of the metallization layers. An anisotropic magnetoresistive (AMR) stack is on the first dielectric layer between vertically aligned portions of an etch stop layer formed on the first dielectric layer and a second dielectric layer formed on the etch stop layer. Vias extend through the first dielectric layer to electrically connect the AMR stack and the contacts. A chemical-mechanical planarization (CMP) stop layer is on the AMR stack. A third dielectric layer is on the CMP stop layer. A passivation layer contacts the second dielectric layer portions, the third dielectric layer, and each opposing end of the AMR stack and the CMP stop layer.

First claim

What is claimed is:

1. A method comprising:
forming a trench in a substrate, wherein:
the substrate comprises an integrated circuit (IC) device, a first dielectric layer, an etch stop layer interposing the IC device and the first dielectric layer, conductive vias extending from the etch stop layer to corresponding contacts of the IC device, and a second dielectric layer interposing the etch stop layer and the IC device; and
the trench extends through the first dielectric layer and the etch stop layer to expose ends of the vias and portions of the second dielectric layer;

forming an anisotropic magnetoresistive (AMR) stack on surfaces exposed by forming the trench, including surfaces of the first and second dielectric layers, the etch stop layer, and the vias;
forming a chemical-mechanical planarization (CMP) stop layer on the AMR stack within the trench;
forming a third dielectric layer over the CMP stop layer; and
performing CMP to remove each portion of the third dielectric layer and the AMR stack disposed above the CMP stop layer.

2. The method of claim 1 wherein the etch stop layer is silicon nitride (SiN).

3. The method of claim 2 wherein the etch stop layer has a thickness of 500 angstroms.

4. The method of claim 1 further comprising, before forming the AMR stack, forming a barrier layer on the surfaces exposed by forming the trench, wherein forming the AMR stack comprises forming the AMR stack on all exposed surfaces of the barrier layer.

5. The method of claim 4 wherein the barrier layer is tantalum nitride (TaN).

6. The method of claim 1 wherein forming the AMR stack comprises forming a layer of permalloy (NiFe) and forming a layer of aluminum nitride (AlN) on the NiFe layer.

7. The method of claim 1 wherein the CMP stop layer is silicon nitride (SiN).

8. The method of claim 7 wherein the CMP stop layer has a thickness of 500 angstroms.

9. The method of claim 1 wherein the third dielectric layer is an oxide having a thickness of 5000 angstroms.

10. The method of claim 1 further comprising forming a passivation (PO) layer over each surface exposed by the CMP.

11. A method of forming an electronic device, comprising:
forming a trench in a first dielectric layer over a semiconductor substrate;
forming an anisotropic magnetoresistive (AMR) stack on sidewalls and a bottom of the trench, the AMR stack including a portion overlying the substrate lateral to the trench;
forming a second dielectric layer within the trench, the second dielectric layer including a portion overlying the substrate lateral to the trench;
removing the portion of the second dielectric layer overlying the substrate lateral to the trench; and
removing the portion of the AMR stack overlying the substrate lateral to the trench,
wherein forming the trench exposes vias that conductively connect to an electronic device formed in or over the semiconductor substrate, and wherein the AMR stack includes a conductive layer that conductively connects to the vias.

12. The method of claim 11 wherein the AMR stack includes a tantalum nitride (TaN) layer in contact with the first dielectric layer, a ferromagnetic layer in contact with the TaN layer, and an aluminum nitride (AlN) layer in contact with the ferromagnetic layer.

13. The method of claim 11 wherein the AMR stack includes a horizontal portion between sidewall portions, and wherein the method further comprises removing the sidewall portions thereby exposing a third dielectric layer that underlies the AMR stack.

14. The method of claim 11 wherein the AMR stack conductively connects to vias that extend through a third dielectric layer that underlies the AMR stack, and wherein the vias conductively connect to an integrated circuit (IC) device that underlies the third dielectric layer.

15. A method of forming an electronic device, comprising:
forming a trench in a first dielectric layer over a semiconductor substrate;
forming an anisotropic magnetoresistive (AMR) stack on sidewalls and a bottom of the trench, the AMR stack including a portion overlying the substrate lateral to the trench;
forming a second dielectric layer within the trench, the second dielectric layer including a portion overlying the substrate lateral to the trench;
removing the portion of the second dielectric layer overlying the substrate lateral to the trench; and
removing the portion of the AMR stack overlying the substrate lateral to the trench,
wherein the AMR stack includes a tantalum nitride (TaN) layer in contact with the first dielectric layer, a ferromagnetic layer in contact with the TaN layer, and an aluminum nitride (AlN) layer in contact with the ferromagnetic layer.

16. A method of forming an electronic device, comprising:
forming a trench in a first dielectric layer over a semiconductor substrate;
forming an anisotropic magnetoresistive (AMR) stack on sidewalls and a bottom of the trench, the AMR stack including a portion overlying the substrate lateral to the trench;
forming a second dielectric layer within the trench, the second dielectric layer including a portion overlying the substrate lateral to the trench;
removing the portion of the second dielectric layer overlying the substrate lateral to the trench; and
removing the portion of the AMR stack overlying the substrate lateral to the trench,
wherein the AMR stack includes a horizontal portion between sidewall portions, and wherein the method further comprises removing the sidewall portions thereby exposing a third dielectric layer that underlies the AMR stack.

17. A method of forming an electronic device, comprising:
forming a trench in a first dielectric layer over a semiconductor substrate;
forming an anisotropic magnetoresistive (AMR) stack on sidewalls and a bottom of the trench, the AMR stack including a portion overlying the substrate lateral to the trench;
forming a second dielectric layer within the trench, the second dielectric layer including a portion overlying the substrate lateral to the trench;
removing the portion of the second dielectric layer overlying the substrate lateral to the trench; and
removing the portion of the AMR stack overlying the substrate lateral to the trench,
wherein the AMR stack conductively connects to vias that extend through a third dielectric layer that underlies the AMR stack, and wherein the vias conductively connect to an integrated circuit (IC) device that underlies the third dielectric layer.

Assignees

• Texas Instruments Inc

Inventors

• Wang Fuchao
• Brannon Christopher Eric
• French William David
• Lee Dok Won

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10N59/00

  Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00 (MRAM devices H10B61/00) · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title

• G01R33/0052

  Manufacturing aspects; Manufacturing of single devices, i.e. of semiconductor magnetic sensor chips (devices based on galvano-magnetic effect or the like H10N50/85) · CPC title

• H10N50/80

  Constructional details · CPC title