Common wire full-wave rectifier circuit

US12068698B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12068698-B2
Application numberUS-202117538544-A
CountryUS
Kind codeB2
Filing dateNov 30, 2021
Priority dateNov 30, 2021
Publication dateAug 20, 2024
Grant dateAug 20, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In an example, a rectifier circuit includes first and second capacitors, first and second current control devices, and a switch. The first current control device is configured to provide an input current to the first capacitor during a positive cycle of an alternating current (AC) input voltage. The second capacitor is configured to store a charge and the switch is configured to couple the second capacitor to a ground terminal so the second capacitor discharges a capacitor current during the positive cycle of the input voltage responsive to the stored charge in the second capacitor. The second current control device is configured to provide the capacitor current to the first capacitor during the positive cycle of the input voltage. The first capacitor is configured to store a charge responsive to the input current and the capacitor current.

First claim

Opening claim text (preview).

What is claimed is: 1. A circuit comprising: a first capacitor; a first current control device configured to provide an input current to the first capacitor during a positive cycle of an alternating current (AC) input voltage; a second capacitor having first and second terminals, the second capacitor configured to store a charge; a switch coupled between the first terminal of the second capacitor and a ground terminal, wherein the switch is configured to discharge the second capacitor during the positive cycle of the input voltage, providing a capacitor current, responsive to the stored charge in the second capacitor; and a second current control device configured to provide current to the first capacitor during the positive cycle of the input voltage, wherein the first capacitor is configured to store a charge responsive to the input current and the capacitor current. 2. The circuit of claim 1 , wherein current flows along a first path from the second terminal of the second capacitor toward the second current control device during the positive cycle of the input voltage, the circuit further comprising: a third current control device; and a fourth current control device, in which the third current control device is configured to provide the input current to the second terminal of the second capacitor along a second path to the fourth current control device during a negative cycle of the input voltage. 3. The circuit of claim 2 , wherein the switch is disabled during the negative cycle of the input voltage. 4. The circuit of claim 3 , wherein the switch includes a field effect transistor (FET) coupled between the first terminal of the second capacitor and the ground terminal, and having a control terminal configured to receive the input voltage. 5. The circuit of claim 4 , wherein the circuit further comprises a gate control circuit coupled to a gate of the FET, and the gate control circuit is configured to activate the FET during the positive cycle of the input voltage. 6. The circuit of claim 5 , wherein the gate control circuit includes: a resistor coupled between an input terminal and the gate of the FET; and a Zener diode coupled between the gate of the FET and a drain of the FET. 7. The circuit of claim 6 , wherein the first, second, third, and fourth respective current control devices are first, second, third and fourth switches, respectively, and the first and second switches are each configured to activate during the positive cycle of the input voltage responsive to respective switch control signals, and the third and fourth switches are each configured to activate during the negative cycle of the input voltage. 8. The circuit of claim 7 , wherein the respective switch control signals are provided by a controller. 9. The circuit of claim 6 , wherein the first, second, third, and fourth current control devices are each diodes. 10. The circuit of claim 9 , wherein the first current control device is coupled to the input terminal, which is configured to receive the input voltage. 11. A system comprising: a rectifier having a rectifier input and a rectifier output, wherein the rectifier input is configured to receive an alternating current (AC) input voltage, the rectifier comprising: a first capacitor; a first current control device configured to provide an input current to the first capacitor during a positive cycle of the AC input voltage; a second capacitor having first and second capacitor terminals, wherein the second capacitor is configured to store a charge; a switch coupled between the first capacitor terminal and a ground terminal, wherein closing the switch discharges the charge stored the second capacitor, providing a capacitor current, during the positive cycle of the input voltage; a second current control device configured to provide the capacitor current to the first capacitor during the positive cycle of the input voltage, and the first capacitor is configured to store a charge responsive to the input current and the capacitor current; and a power converter having a converter input and a converter output, wherein the converter input is coupled the rectifier output, and the power converter is configured to provide a regulated output voltage at the converter output responsive a direct current (DC) output voltage at the rectifier output. 12. The system of claim 11 , wherein the power converter is a direct-current-to-direct-current (DC-DC) integrated circuit (IC), and the DC-DC IC includes the first current control device, the second current control device, and the switch. 13. The system of claim 12 , further comprising a step-down transformer configured to provide the AC input voltage at the rectifier input, in which the AC input voltage is provided by an AC source. 14. The system of claim 13 , wherein current flows along a first path from the second capacitor terminal toward the second current control device during the positive cycle of the input voltage, the system further comprising: a third current control device; and a fourth current control device, in which the third current control device is configured to provide current to the second capacitor terminal along a second path to the fourth current control device during a negative cycle of the AC input voltage; wherein the switch is disabled during the negative cycle of the AC input voltage. 15. A circuit comprising: a first current control device having a first current control input and a first current control output; a second current control device having a second current control input and a second current control output, wherein the second current control input is coupled to the first current control output; a third current control device having a third current control input and a third current control output, wherein the third current control output is coupled to the second current control output; a fourth current control device having a fourth current control input and a fourth current control output, wherein the fourth current control output is coupled to the third current control input, and the fourth current control input is coupled to a common terminal; a first capacitor having first and second capacitor terminals, wherein the first capacitor terminal is coupled to the second current control output, and the second capacitor terminal is coupled to the common terminal; a second capacitor having third and fourth capacitor terminals, wherein the third capacitor terminal is coupled to the first current control input, and the fourth capacitor terminal is coupled to third current control input and to the fourth current control input; and a switch coupled between the third capacitor terminal and the common terminal. 16. The circuit of claim 15 , wherein the switch includes a transistor having a gate and a drain, in which the drain is the first current control input, the circuit further comprising a gate control circuit having a gate control output coupled to the gate of the transistor. 17. The circuit of claim 16 , wherein the gate control circuit includes: a resistor coupled between an input terminal and the gate of the transistor, and a Zener diode coupled to between the gate of the transistor and the drain of the transistor. 18. The circuit of claim 15 , wherein each of the first, second, third, and fourth current control devices is a respective diode, and the switch is a transistor. 19. The circuit of claim 18 , wherein: the second current control device is configured to provide an input current to the first capacitor during a

Assignees

Inventors

Classifications

  • Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

  • Conversion of DC power input into DC power output · CPC title

  • Electrical aspects, e.g. circuits · CPC title

  • using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

  • comprising a passive stage to generate a rectified sinusoidal voltage and a controlled switching element in series between such stage and the output · CPC title

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What does patent US12068698B2 cover?
In an example, a rectifier circuit includes first and second capacitors, first and second current control devices, and a switch. The first current control device is configured to provide an input current to the first capacitor during a positive cycle of an alternating current (AC) input voltage. The second capacitor is configured to store a charge and the switch is configured to couple the seco…
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification H02M7/217. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 20 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).