Display device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12068334-B2
Application number	US-202017039474-A
Country	US
Kind code	B2
Filing date	Sep 30, 2020
Priority date	Nov 6, 2019
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

According to some embodiments of the present disclosure, a display device includes an active pattern including a metal oxide, a gate electrode overlapping the active pattern, a first capacitor electrode spaced apart from the active pattern and including a conductive oxide, and a second capacitor electrode on the first capacitor electrode.

First claim

What is claimed is:

1. A display device comprising:
an active pattern disposed on a base substrate and including a metal oxide;
a gate electrode overlapping the active pattern;
a first capacitor electrode including a conductive oxide;
a dummy semiconductor pattern between the first capacitor electrode and a planarized upper surface of the base substrate that faces the dummy semiconductor pattern and having a conductivity different from a conductivity of the first capacitor electrode, wherein an entire portion of a lower surface of the first capacitor electrode directly contacts an upper surface of the dummy semiconductor pattern without an intervening layer between the entire portion of the lower surface of the first capacitor electrode and the upper surface of the dummy semiconductor pattern;
an insulation layer disposed on the active pattern and the dummy semiconductor pattern, the insulation layer directly contacting a side surface of the active pattern and a side surface of the dummy semiconductor pattern; and
a second capacitor electrode on the first capacitor electrode, the first capacitor electrode being between the dummy semiconductor pattern and the second capacitor electrode,
wherein a thickness between a lower surface and the upper surface of the dummy semiconductor pattern is at least as great as a thickness between a lower surface and the upper surface of the active pattern.

2. The display device of claim 1 , wherein the metal oxide includes tin.

3. The display device of claim 2 , wherein the metal oxide includes tin and gallium.

4. The display device of claim 3 , wherein the metal oxide includes at least one selected from among the group consisting of indium tin gallium oxide, indium tin gallium zinc oxide, and tin aluminum gallium oxide.

5. The display device of claim 2 , wherein the conductive oxide includes indium and tin.

6. The display device of claim 1 , wherein the conductive oxide is crystalline.

7. The display device of claim 1 , further comprising:
a gate insulation pattern between the active pattern and the gate electrode; and
a dielectric pattern between the first capacitor electrode and the second capacitor electrode and formed from a same layer as the gate insulation pattern.

8. The display device of claim 1 , further comprising a connection line to transfer a constant voltage to the first capacitor electrode.

9. The display device of claim 8 , wherein the connection line extends over the second capacitor electrode to form a third capacitor electrode overlapping the second capacitor electrode.

10. The display device of claim 1 , wherein the second capacitor electrode is electrically connected to the gate electrode.

11. The display device of claim 1 , wherein the second capacitor electrode and the gate electrode are in a same pattern.

12. The display device of claim 1 , wherein the dummy semiconductor pattern comprises a same material as the active pattern comprises.

Assignees

• Samsung Display Co Ltd

Inventors

• Jeon Kyung Jin
• Kim Eok Su
• Park Joon Seok
• Koo So Young
• Kim Tae Sang
• Lim Jun Hyung

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/481 Primary

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title