Address dependent wordline timing in asynchronous static random access memory

Patent metadata

Field	Value
Publication number	US-12068024-B2
Application number	US-202217734045-A
Country	US
Kind code	B2
Filing date	Apr 30, 2022
Priority date	Apr 30, 2022
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.

First claim

We claim:

1. A memory device comprising:
a wordline controller configured to activate a wordline with a pulse width determined by one or more significant bits of an applied address in combination with at least two desired data error rates;
at least one memory array arranged as a sequence of columns of data, each column of data activated by an associated wordline, the activated wordline causing data from a column of memory cells associated with the wordline to be asserted to bitlines coupled to an input/output driver;
the wordline controller configured to cause an associated wordline pulse width to be longer for an address value which has a longer associated wordline than an address value which has a comparatively shorter associated wordline.

2. The memory device of claim 1 where the at least one memory array comprises a top memory cell array and a bottom memory cell array.

3. The memory device of claim 1 where the at least one memory array is configured to provide a high value address a greater distance from the wordline controller than a low value address.

4. The memory device of claim 1 where the at least one memory array is configured to have a wordline signal path length which is shorter for a memory array data most significant bit (MSB) than for a memory array data least significant bit (LSB) for a column of data.

5. The memory device of claim 1 where the bitlines are configured to output multiples of 8 bits of data.

6. The memory device of claim 1 where the bitlines are configure to output 32 bits of data arranged as four eight bit bytes which are individually selectable as output data.

7. The memory device of claim 1 where the at least two desired data error rates include a higher data error rate and a lower data error rate selected from: an error rate of approximately 10% MSB data errors, an error rate of approximately 1% MSB data errors, an error rate of approximately 0.1% MSB data errors, and an error rate of less than 0.00034% MSB data errors.

8. The memory device of claim 7 where for a given data error rate and a given address, the MSB data error rate is less than a corresponding LSB data error rate.

9. The memory device of claim 1 where the at least two data error rates are selected from: a high error rate of 2% to 15% MSB data error rate, a medium error rate of 0.5% to 2% MSB data error rate, a low error rate of 0.005% to 0.5% MSB data error rate, and very low error rate of less than 0.00034% data errors.

10. A memory array comprising:
a top memory cell array accessed by activating a wordline which causes the top memory cell array to output data onto one or more bitlines;
a bottom memory cell array accessed by activating a wordline which causes bottom memory cell array to output data onto one or more bitlines;
a wordline controller configured to examine output data from the one or more bitlines and one or more most significant bits of an applied address, the wordline controller modifying a wordline pulse width until one of four error rates occurs:
a high error rate where a most significant bit (MSB) of data in a particular memory cell has an error rate in the range of 2% to 15%, or approximately 10%;
a moderate error rate where the MSB of data in the particular memory cell has an error rate in the range of 0.5% to 2%, or approximately 1%;
a low error rate where the MSB of data in the particular memory cell has an error rate in the range of 0.005% to 0.5%, or approximately 0.1%; and
a very low error rate where the MSB of data in the particular memory cell has an error rate less than 0.00034%;
and where a selected data error rate is maintained over an available applied address range.

11. The memory device of claim 10 where the at least one memory array is configured to provide a high value address a greater distance from the wordline controller than a low value address.

12. The memory device of claim 10 where the at least one memory array is configured to have a wordline signal path length which is shorter for a most significant bit (MSB) than a wordline signal path length for a least significant bit (LSB) for a column of data.

13. The memory device of claim 10 where the one or more bitlines comprise multiples of 8 bits of data.

14. The memory device of claim 10 where the one or more bitlines provide 32 bits of data arranged as four eight bit bytes which are individually selectable as output data.

15. The memory device of claim 10 where the four error rates include error rates of approximately 10% MSB errors, approximately 1% MSB errors, approximately 0.1% MSB errors, and less than 0.00034% MSB errors.

16. The memory device of claim 10 where for a given error rate and a given address, the MSB data error rate is less than a corresponding LSB data error rate.

17. The memory device of claim 10 where the four error rates are a high error rate of 2% to 15% MSB error rate, a medium error rate of 0.5% to 2% MSB error rate, a low error rate of 0.005% to 0.5%, and very low error rate of less than 0.00034% error rate.

Assignees

• Ceremorphic Inc

Inventors

• Chesavage Jay A
• Wiser Robert
• Surana Neelam

Classifications

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C7/1039

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title