Compact pixel driver for micro-LED displays

Patent metadata

Field	Value
Publication number	US-12067933-B2
Application number	US-202318333374-A
Country	US
Kind code	B2
Filing date	Jun 12, 2023
Priority date	Jan 24, 2023
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

A micro-LED display has an array of separately controllable micro-LEDs and corresponding pixel drivers. The pixel drivers have pulse-width modulation (PWM) generator circuits for the LEDs. The PWM generator circuits include the following. N input nodes are coupled to receive N control bits that determine a brightness of the LEDs. An output node is coupled to output the drive signal to the LEDs. Each of N transistors are connected between one of the input nodes and the output node. Each transistor is controlled by a clock signal CKn and couples the input node to the output node as controlled by the clock signal CKn.

First claim

What is claimed is:

1. A micro-LED display comprising:
an array of separately controllable micro-LEDs arranged as pixels for the display; and
a plurality of pixel drivers that drive the pixels of micro-LEDs, each pixel driver comprising:
a local memory that stores bits that determine brightness of the micro-LEDs for that pixel driver;
one or more pulse width modulation (PWM) generator circuits that drive the micro-LEDs according to N bits B n stored in the local memory, each PWM generator circuit comprising N first transistors of a first polarity, each first transistor having a source, drain and gate; wherein the source and drain of each of the N first transistors are connected between one of the stored bits of the local memory and a drive node that is connected to the micro-LEDs, and the gate of each of the N first transistors is controlled by a signal based on a clock signal CK n corresponding to bit B n ; and
reset transistors coupled between the drive nodes and a supply node.

2. The micro-LED display of claim 1 wherein the PWM generator circuits for multiple pixel drivers all receive the same clock signals CK n .

3. The micro-LED display of claim 2 wherein pulse widths of the clock signals CK n increase by powers of 2 for different values of n.

4. The micro-LED display of claim 1 wherein the reset transistors are turned on during a dead time between clock signals CK n .

5. The micro-LED display of claim 1 further comprising:
a clock source that generates the clock signals CK n and a reset source that generates reset signals for the reset transistors, wherein the clock source and the reset source are located outside an area occupied by the pixel drivers; and
a distribution network to distribute the clock signals CK n and the reset signals from the clock source and the reset source to the PWM generator circuits.

6. The micro-LED display of claim 1 wherein the local memory and PWM generator circuits occupy an area not more than the array of micro-LEDs.

7. The micro-LED display of claim 1 wherein the local memory and PWM generator circuits are positioned underneath the array of micro-LEDs.

8. The micro-LED display of claim 1 wherein the array of micro-LEDs has a pitch of not more than 4 μm.

9. The micro-LED display of claim 1 wherein each PWM generator circuit includes not more than 6N transistors.

10. A micro-LED display comprising:
an array of separately controllable micro-LEDs arranged as pixels for the display; and
a plurality of pixel drivers that drive the pixels of micro-LEDs, each pixel driver comprising:
a local memory that stores bits that determine brightness of the micro-LEDs for that pixel driver; and
one or more pulse width modulation (PWM) generator circuits that drive the micro-LEDs according to N bits B n stored in the local memory, each PWM generator circuit comprising N first transistors of a first polarity, each first transistor having a source, drain and gate: wherein the source and drain of each of the N first transistors are connected between one of the stored bits of the local memory and a drive node that is connected to the micro-LEDs, and the gate of each of the N first transistors is controlled by a signal based on a clock signal CK n corresponding to bit B n ;
wherein each PWM generator circuit further comprises: N second transistors of a polarity opposite of the first polarity, each second transistor having a source, drain and gate; wherein the source and drain of each of the N second transistors is connected between one of the stored bits of the local memory and the drive node, and the gate of each of the N second transistors is controlled by a signal that is a complement of the signal that controls the corresponding first transistor.

11. The micro-LED display of claim 1 wherein, for each PWM generator circuit, not more than one clock signal CK n is asserted at any time.

12. The micro-LED display of claim 11 wherein the PWM generator circuits are not capable of resolving conflicts if more than one clock signal CK n is asserted at any time.

13. The micro-LED display of claim 1 wherein the PWM generator circuits do not contain any Boolean logic gates.

14. The micro-LED display of claim 1 wherein, for each bit B n , the local memory storing that bit and the first transistor connected to that bit are implemented as a standard memory cell from a cell library.

15. The micro-LED display of claim 14 wherein the standard memory cell includes a read port and a read control node; wherein the stored bit is read from the read port according to a control signal applied to the read control node, and the clock signal CK n is applied to the read control node.

16. A micro-LED display having a pulse-width modulation (PWM) generator circuit for one or more LEDs in the display, the PWM generator circuit comprising:
N input nodes coupled to receive N bits B n that determine a brightness of the one or more LEDs;
an output node coupled to drive the one or more LEDs;
N first transistors of a first polarity, each first transistor having a source, drain and gate; wherein the source and drain of each of the N first transistors are connected between one of the input nodes and the output node, and the gate of each of the N first transistors is controlled by a signal based on a clock signal CK n corresponding to bit B n ; and
N second transistors of a polarity opposite of the first polarity, each second transistor having a source, drain and gate: wherein the source and drain of each of the N second transistors is connected between one of the input nodes and the output node, and the gate of each of the N second transistors is controlled by a signal that is a complement of the signal that controls the corresponding first transistor.

17. The micro-LED display of claim 16 wherein the PWM generator circuit includes not more than 2N transistors between the N input nodes and the output node.

18. The micro-LED display of claim 16 wherein the PWM generator circuit includes not more than N transistors between the N input nodes and the output node.

19. A micro-LED display comprising:
an array of separately controllable micro-LEDs arranged as pixels for the display;
a plurality of pixel drivers that drive the pixels of micro-LEDs, each pixel driver comprising:
local memory that stores bits that determine brightness of the micro-LEDs for that pixel driver; and
one or more PWM generator circuits that drive the micro-LEDs according to the bits stored in the local memory, each PWM generator circuit comprising a multiplexer that receives bits from the local memory as input signals, receives corresponding clock signals CK n as select signals, and outputs a drive signal to at least one corresponding micro-LEDs; and
a reset transistor that is asserted during programming the local memory.

Assignees

• Tectus Corp

Inventors

• Hekmat Mohammad
• Winoto Renaldi

Classifications

• G09G3/2014 Primary

  by modulation of the duration of a single pulse during which the logic level remains constant · CPC title

• G09G2300/0857

  Static memory circuit, e.g. flip-flop · CPC title

• G09G2320/0626

  for control of overall brightness · CPC title

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title