Multi-core processing and memory arrangement

Patent metadata

Field	Value
Publication number	US-12066976-B2
Application number	US-202318239040-A
Country	US
Kind code	B2
Filing date	Aug 28, 2023
Priority date	Jan 29, 2021
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

This invention provides a generalized electronic computer architecture with multiple cores, memory distributed amongst the cores (a core-local memory). This arrangement provides predictable, low-latency memory response time, as well as a flexible, code-supplied flow of memory from one specific operation to another (using an operation graph). In one instantiation, the operation graph consists of a set of math operations, each accompanied by an ordered list of one or more input addresses. Input addresses may be specific addresses in memory, references to other math operations in the graph, or references to the next item in a particular data stream, where data streams are iterators through a continuous block of memory. The arrangement can also be packaged as a PCIe daughter card, which can be selectively plugged into a host server/PC constructed/organized according to traditional von Neumann architecture.

First claim

What is claimed is:

1. A method for processing data with a multi-core computer processing arrangement comprising:
providing a plurality of core-memory pairs with, respectively, a plurality of processing cores, each having a discrete, respective, core-local memory associated therewith interconnected for data transfer therebetween; and
transferring data between each of the processing cores and a core-local memory with switching arrangements and a data bus that interconnect the core-memory pairs to each other, respectively, wherein the core-memory pairs are substantially free of caches for data transferred therebetween;
operating a code-supplied flow of core-memory pairs from one specific operation to another using an operation graph; and
defining the operation graph as a set of mathematical operations, each accompanied by an ordered list of one or more input addresses.

2. The method as set forth in claim 1 , further comprising, locating at least one of the core-memory pairs on a single die.

3. The method as set forth in claim 1 , further comprising, defining the input addresses as specific addresses in memory, references to other math operations in the graph, or references to a next item in a data stream, and iterating data streams through a continuous block of the core-local memory.

4. The method as set forth in claim 3 , further comprising, defining the core-memory pairs by an autonomous module arrangement.

5. The method as set forth in claim 1 , further comprising, locating at least one of the core-memory pairs on at least one separate die.

6. The method as set forth in claim 1 , further comprising, mounting a die containing a plurality of the core-memory pairs on a PCIe daughter card, which is adapted to be selectively plugged into a host server/PC having a host processor constructed according to a traditional von Neumann architecture.

7. The method as set forth in claim 1 , further comprising, operating a compiler for program data processed by the core-memory pairs on at least one of (a) one or more of the core-memory pairs and (b) the host processor.

8. The method as set forth in claim 7 , further comprising, storing program data with respect to, and operating the program data on, the host processor, to initiate compilation and computation.

9. The method as set forth in claim 7 , further comprising, basing operations carried out by the host processor and the core-memory pairs on an existing RISC-based instruction set.

10. The method as set forth in claim 9 , further comprising, communication an operation graph to each of the core-memory pairs through store operations to specific, pre-reserved false memory addresses within the core-memory pairs.

11. The method as set forth in claim 1 , further comprising, transferring memory content and operations to the each of the core-memory pairs through store operations from a von Neumann processor on a host computer through a standard bus interface.

12. A method for computing comprising:
providing a plurality of processing cores, each having a discrete, respective, core-local memory associated therewith interconnected for data transfer therebetween so as to define a plurality of respective core-memory pairs;
providing switching arrangements and a data bus that interconnect the core-memory pairs to each other for data transfer between each of the processing cores and a core-local memory, respectively, wherein the core-memory pairs are substantially free of caches for data transferred therebetween; and
operating the core-memory pairs based upon an operation graph and a source of the operation graph is based upon (a) program data that converts SIMD operations to operations written in a predetermined instruction set, and (b) existing APIs that are recreated as operation graphs, and for which new APIs are used as drop-in replacements for the existing APIs.

13. The method as set forth in claim 12 , further comprising, locating at least one of the core-memory pairs on a single die.

14. The method as set forth in claim 13 , further comprising, defining the input addresses as specific addresses in memory, references to other math operations in the graph, or references to a next item in a data stream, and iterating the data streams through a continuous block of the core-local memory.

15. The method as set forth in claim 12 , further comprising, defining the core-memory pairs by an autonomous module arrangement.

16. The method as set forth in claim 12 , further comprising, locating at least one of the core-memory pairs on at least one separate die.

17. The method as set forth in claim 12 , further comprising, mounting a die containing a plurality of the core-memory pairs on a PCIe daughter card, which is adapted to be selectively plugged into a host server/PC having a host processor constructed according to a traditional von Neumann architecture.

18. The method as set forth in claim 17 , further comprising, operating a compiler for program data processed by the core-memory pairs on at least one of (a) one or more of the core-memory pairs and (b) the host processor.

19. The method as set forth in claim 17 , further comprising, storing program data with respect to, and operating the program data on, the host processor, to initiate compilation and computation.

20. The method as set forth in claim 17 , further comprising, basing operations carried out by the host processor and the core-memory pairs on an existing RISC-based instruction set.

Assignees

• Dartmouth College

Inventors

• Bowen Elijah F W
• Granger Jr Richard H

Classifications

• G06F15/7896

  Modular architectures, e.g. assembled from a number of identical packages · CPC title

• G06F15/7839

  with memory · CPC title

• G06F15/7825

  Globally asynchronous, locally synchronous, e.g. network on chip · CPC title

• G06F2015/763

  ASIC · CPC title

• G06F15/80 Primary

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title