Data processing device, image reading apparatus, image forming apparatus, and method for processing data

Patent metadata

Field	Value
Publication number	US-12066854-B2
Application number	US-202017766254-A
Country	US
Kind code	B2
Filing date	Nov 20, 2020
Priority date	Dec 13, 2019
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

A data processing device comprises: a data receiver to receive data to be processed, an external clock, and a unit control signal determining a processing unit for the data to be processed from an outside, the data receiver including a PLL circuit to receive the external clock; a clock abnormality detector to operate based on a clock of a system different from a system of the external clock and detect abnormality of the external clock based on a lock signal output from the PLL circuit; and a data processing controller to control processing of the data. When abnormality of the external clock is detected, the data processing controller stops taking in the data to be processed, and when the external clock becomes normal again, take in the unit control signal and resume taking in the data to be processed.

First claim

The invention claimed is:

1. A data processing control device comprising:
a data receiver configured to receive data to be processed, an external clock generated externally from the data processing control device, and a unit control signal determining a processing unit as an amount of the data to be processed, the data receiver including a phase locked loop (PLL) circuit configured to receive the external clock;
a clock abnormality detector configured to receive a lock signal output from the PLL circuit and the unit control signal and operate based on a clock different from the external clock and output a write synchronization signal, a read synchronization signal and a write mask signal based on the lock signal and the unit control signal;
a memory write controller configured to produce a write control signal based on the write synchronization signal and the write mask signal;
a memory read controller configured to produce a read control signal based on the read synchronization signal; and
a first memory and a second memory configured to alternatively write and read the data to be processed based on the write control signal and the read control signal,
wherein when abnormality of the external clock occurs, the memory write controller produces the write control signal to stop writing of the data to be processed in the first memory or the second memory, and
when the external clock becomes normal again, to take in the unit control signal, the memory write controller produces the write control signal to write the data to be processed in the first memory or the second memory.

2. The data processing control device according to claim 1 , wherein, when the clock abnormality detector detects abnormality of the external clock, the data processing circuitry stops taking in the unit control signal.

3. The data processing control device according to claim 1 , wherein the data to be processed includes image data, and the unit control signal includes a line synchronization signal determining a line unit for the image data.

4. The data processing control device according to claim 1 , wherein the data to be processed includes image data, and the unit control signal includes a page synchronization signal determining a page unit for the image data.

5. The data processing control device according to claim 1 , wherein the data to be processed is transmitted by a low voltage differential signaling (LVDS) system, and the data receiver configured to receive the data to be processed includes an LVDS receiver.

6. An image reading apparatus configured to optically read an image, the image reading apparatus comprising:
data acquisition circuitry configured to transmit optically read image data together with a clock signal; and
a data processing control device according to claim 1 , the data processing control device being configured to receive the image data as the data to be processed, the clock signal as the external clock, and the unit control signal determining the processing unit as the amount of the image data to be processed from the data acquisition circuitry, and execute processing on the image data.

7. An image forming apparatus comprising:
an image former configured to form an image on a recording medium using the data processed by the data processing control device according to claim 1 .

8. The image forming apparatus according to claim 7 , further comprising:
an automatic document feeder (ADF) to automatically provide pages of documents to the image former to form images of the pages of the documents.

9. The image forming apparatus according to claim 7 , wherein the image forming apparatus is a multifunction peripheral.

10. The data processing control device according to claim 1 , wherein the clock different from the external clock is generated internally in the data processing control device.

11. The data processing control device according to claim 10 , wherein the clock different from the external clock is generated by an oscillator of the data processing control device.

12. A method for processing data performed by a data processing control device, the method comprising:
receiving data to be processed, an external clock generated externally from the data processing control device, and a unit control signal determining a processing unit as an amount of the data to be processed, the external clock being received by a PLL circuit;
receiving a lock signal from the PLL circuit and the unit control signal and operating based on a clock different from the external clock and outputting a write synchronization signal, a read synchronization signal and a write mask signal based on the lock signal and the unit control signal;
producing a write control signal based on the write synchronization signal and the write mask signal;
producing a read control signal based on the read synchronization signal; and
alternatively write and read the data to be processed to or from a first memory and a second memory based on the write control signal and the read control signal,
wherein, when abnormality of the external clock occurs, the method further comprises:
producing the write control signal to stop writing of the data to be processed in the first memory or in the second memory, and
when the external clock becomes normal again, taking in the unit control signal, producing the write control signal to write the data to be processed in the first memory or the second memory.

Assignees

• Tsukahara Hajime
• Sasa Tomohiro
• Ricoh Co Ltd

Inventors

• Tsukahara Hajime
• Sasa Tomohiro

Classifications

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/0751 Primary

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F11/0733

  in a data processing system embedded in an image processing device, e.g. printer, facsimile, scanner · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title