Embedded PHY (EPHY) IP core for FPGA

Patent metadata

Field	Value
Publication number	US-12066488-B2
Application number	US-202318197902-A
Country	US
Kind code	B2
Filing date	May 16, 2023
Priority date	Feb 28, 2020
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYS (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC) production cycles.

First claim

What is claimed is:

1. A testing device, comprising:
a field programmable gate array (FPGA); and
an embedded physical layer (EPHY), the EPHY including:
a logic portion having a first logical phy and a second logical phy, wherein the logic portion is disposed in the FPGA, and wherein the logic portion communicates with the FPGA through the first and second logical phys; and
a glue hardware portion, wherein the logic portion communicates with a device under test (DUT) through the glue hardware portion, the glue hardware portion including:
a first differential amplifier; and
a first multiplexer (MUX) coupled to the first differential amplifier and the FPGA via a first line, wherein the testing device is capable of receiving and sending signals to and from the DUT at a first speed, wherein the testing device is capable of receiving and sending signals to and from the DUT at a second speed, wherein the second speed is greater than the first speed, and wherein the first differential amplifier is configured to reduce or increase the signals sent and received at the first speed or the signals sent and received at the second speed.

2. The testing device of claim 1 , wherein the glue hardware further comprises:
a second differential amplifier; and
a second MUX coupled to the second differential amplifier.

3. The testing device of claim 2 , wherein the first MUX and the first differential amplifier are coupled to the FPGA using a first transmission line, wherein the second MUX and the second differential amplifier are coupled to the FPGA using a second transmission line.

4. The testing device of claim 2 , further comprising:
a first receiving line coupled to the FPGA;
a third differential amplifier coupled to the first receiving line; and
a third MUX coupled to the third differential amplifier.

5. The testing device of claim 4 , further comprising:
a second receiving line coupled to the FPGA;
a fourth differential amplifier coupled to the second receiving line; and
a fourth MUX coupled to the fourth differential amplifier.

6. The testing device of claim 1 , wherein the glue hardware further comprises an impedance detection unit coupled to the FPGA.

7. The testing device of claim 6 , wherein the impedance detection unit comprises an adjustable regulator and one or more comparators.

8. A testing device, comprising:
a field programmable gate array (FPGA) comprising a controller; and
an embedded physical layer (EPHY) coupled to the controller, the EPHY including:
a logic portion comprising a low speed interface and a high speed interface, wherein the logic portion is disposed in the FPGA, and wherein the logic portion communicates with the FPGA through the low speed interface and the high speed interface; and
a glue hardware portion, wherein the logic portion communicates with a device under test (DUT) through the glue hardware portion, the glue hardware portion comprising:
a plurality of transmission multiplexers (MUXs);
a plurality of receiving MUXs; and
a plurality of differential amplifiers, wherein the testing device is capable of receiving and sending signals to and from the DUT at a first speed, wherein the testing device is capable of receiving and sending signals to and from the DUT at a second speed, wherein the second speed is greater than the first speed, and wherein:
the low speed interface is coupled to a first transmission MUX of the plurality of transmission MUXs;
the low speed interface is coupled to a first receiving MUX of the plurality of receiving MUXs;
the high speed interface is coupled to a second transmission MUX of the plurality of transmission MUXs; and
the high speed interface is coupled to a second receiving MUX of the plurality of receiving MUXs.

9. The testing device of claim 8 , wherein the glue hardware portion is connected to the FPGA through one or more transmission lines or one or more receiving lines.

10. The testing device of claim 8 , wherein the glue hardware portion further comprises:
a first differential amplifier of the plurality of differential amplifiers coupled to the second transmission MUX; and
a second differential amplifier of the plurality of differential amplifiers coupled to the second receiving MUX.

11. The testing device of claim 8 , wherein the glue hardware further comprises:
an impedance detection unit coupled to the FPGA; and
a phase lock loop (PLL) coupled to the FPGA.

12. The testing device of claim 11 , wherein the first receiving MUX and the second receiving MUX are coupled to the impedance detection unit.

13. The testing device of claim 8 , wherein the glue hardware portion further comprises:
a third differential amplifier of the plurality of differential amplifiers coupled to the first transmission MUX; and
a fourth differential amplifier of the plurality of differential amplifiers coupled to the first receiving MUX.

14. The testing device of claim 8 , further comprising one or more storage units coupled to the FPGA.

15. A testing device, comprising:
a field programmable gate array (FPGA) comprising a controller; and
an embedded physical layer (EPHY) coupled to the controller, the EPHY including:
a logic portion comprising a low speed interface and a high speed interface, wherein the logic portion is disposed in the FPGA, and wherein the logic portion communicates with the FPGA through the low speed interface and the high speed interface; and
a glue hardware portion, wherein the logic portion communicates with a device under test (DUT) through the glue hardware portion, the glue hardware portion comprising:
a plurality of transmission multiplexers (MUXs);
a plurality of receiving MUXs; and
a plurality of differential amplifiers, wherein the testing device is capable of receiving and sending signals to and from the DUT at a first speed, wherein the testing device is capable of receiving and sending signals to and from the DUT at a second speed, wherein the second speed is greater than the first speed, and wherein:
the low speed interface is coupled to a first transmission MUX of the plurality of transmission MUXs and a first differential amplifier of the plurality of differential amplifiers;
the low speed interface is coupled to a first receiving MUX of the plurality of receiving MUXs and a second differential amplifier of the plurality of differential amplifiers;
the high speed interface is coupled to a second transmission MUX of the plurality of transmission MUXs and a third differential amplifier of the plurality of differential amplifiers; and
the high speed interface is coupled to a second receiving MUX of the plurality of receiving MUXs and a fourth differential amplifier of the plurality of differential amplifiers.

16. The testing device of claim 15 , wherein the glue hardware portion is connected to the FPGA through one or more transmission lines or one or more receiving lines.

17. The testing device of claim 15 wherein the glue hardware further comprises:
an impedance detection unit coupled to the FPGA; and
a phase lock loop (PLL) coupled to the FPGA.

18. The testing device of claim 17 , wherein the first receiving MUX and the second receiving MUX are coupled to the impedance detection unit.

19. The testing device of claim 15 , further comprising one or more storage units coupled to the FPGA.

Assignees

• Western Digital Tech Inc
• Sandisk Technologies Inc

Inventors

• Ganon Doron
• Lerner Eitan

Classifications

• G06F30/347 Primary

  Physical level, e.g. placement or routing · CPC title

• G06F7/64

  Digital differential analysers, i.e. computing devices for differentiation, integration or solving differential or integral equations, using pulses representing increments; Other incremental computing devices for solving difference equations (G06F7/70 takes precedence; differential analysers using hybrid computing techniques G06J1/02 {; DDA application in numerical control G05B19/18}) · CPC title

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• G01R31/002

  where the device under test is an electronic circuit · CPC title

• G01R31/31908

  Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns · CPC title