Buried connection line for peripheral area of a memory device

Patent metadata

Field	Value
Publication number	US-12063797-B2
Application number	US-202117513489-A
Country	US
Kind code	B2
Filing date	Oct 28, 2021
Priority date	Oct 28, 2021
Publication date	Aug 13, 2024
Grant date	Aug 13, 2024

Abstract

An apparatus includes a substrate and a memory cell array disposed on the substrate. The apparatus also includes a logic cell disposed on the substrate in a peripheral region adjacent the memory cell array. The apparatus further includes a trench isolation region disposed in the substrate in the peripheral region. The trench isolation region either separates a first active area of the logic cell from a second active area of the logic cell or separates the logic cell from an adjacent logic cell. The logic cell includes a connection line that is buried within the trench isolation region. The connection line can be formed as an extension of a buried word line in the memory cell array region during a same fabrication process that forms the corresponding buried word line. By extending the buried word line into the peripheral region, the buried connection line can be formed without additional processing.

First claim

We claim:

1. An apparatus, comprising:
a substrate;
a memory cell array disposed on the substrate;
a logic cell disposed on the substrate in a peripheral region adjacent the memory cell array; and
a trench isolation region disposed in the substrate in the peripheral region, the trench isolation region separating a first active area of the logic cell from a second active area of the logic cell,
wherein the logic cell includes a connection line that is buried within the trench isolation region between the first and second active areas, the connection line corresponding to a signal connection line.

2. The apparatus of claim 1 , wherein the buried connection line is an extension of a buried word line formed during a same fabrication process such that the buried connection line linearly aligns with the buried word line.

3. The apparatus of claim 1 , wherein the buried connection line includes a metal layer and is connected to a component in at least one of the first active area or the second active area via a local interconnection contact.

4. The apparatus of claim 1 , wherein the signal connection line is for transmitting at least one of a data signal, a clock signal, or a command signal to the logic cell, and
wherein the first active area is a PMOS region and the second active area is a NMOS region.

5. The apparatus of claim 1 , further comprising:
a second trench isolation region that separates the logic cell from an adjacent logic cell; and
a second buried connection line disposed within the second trench isolation region,
wherein the second buried connection line is a power connection line connected to a power source.

6. The apparatus of claim 1 , wherein the apparatus includes a second trench isolation region in the peripheral region,
wherein the signal connection line is for transmitting at least one of a data signal, a clock signal, or a command signal to the logic cell, and
wherein the second trench isolation region separates the logic cell from an adjacent logic cell and includes a second buried connection line that is a power connection line connected to a power source.

7. The apparatus of claim 1 , wherein a cell height of the logic cell is less than a cell height of a standard logic cell that does not include a buried connection line, the standard logic cell having a same number of connection lines as the logic cell.

8. The apparatus of claim 1 , wherein a cell height of the logic cell is same as a cell height of a standard logic cell that does not include a buried connection line, and
wherein the logic cell has a greater number of connection lines than the standard logic cell.

9. The apparatus of claim 1 , wherein the logic cell corresponds to a standard cell configuration in an automated routing program.

10. The apparatus of claim 1 , wherein the trench isolation region is a shallow trench isolation.

11. A method, comprising:
forming a logic cell on a substrate in a periphery region adjacent a memory cell array;
forming a trench isolation region in the substrate in the periphery region, the trench isolation region separating a first active area of the logic cell from a second active area of the logic cell; and
forming a buried connection line within the trench isolation region between the first and second active areas, the buried connection line corresponding to a signal connection line.

12. The method of claim 11 , wherein the forming of the buried connection line includes forming a buried word line during a same fabrication process such that the buried word line is an extension of the buried word line.

13. The method of claim 11 , further comprising:
forming a local interconnection contact to connect the buried connection line to a component in at least one of the first active area or the second active area.

14. The method of claim 11 , wherein the forming the buried connection line includes:
forming a connection line pattern on a photoresist layer on at least one of the substrate or the trench isolation region,
etching to a predetermined depth to create a connection line trench in the at least one of the substrate or the trench isolation region,
depositing a metal in the connection line trench to form a metal layer,
performing a chemical mechanical planarization process on the deposited metal layer, and
depositing a nitride isolation layer on the metal layer.

15. The method of claim 14 , wherein the forming the buried connection line further includes depositing a polysilicon layer on the metal layer prior to the deposition of the nitride isolation layer.

16. The method of claim 14 , wherein a local interconnection contact to connect the buried connection line to a component in at least one of the first active area or the second active area is created by,
forming a contact pattern on a photoresist layer deposited on the buried connection line,
etching through the nitride isolation layer to create a contact trench at a depth that exposes at least one of the metal layer or a polysilicon layer deposited on the metal layer,
depositing a second metal in the contact trench to form a metal column, and
performing a chemical mechanical planarization process on the deposited metal column.

17. The method of claim 11 , further comprising:
etching a segment of the buried connection line that extends into a gap region between the peripheral region and the memory cell array.

18. The method of claim 11 , wherein the signal connection line is for transmitting at least one of a data signal, a clock signal, or a command signal to the logic cell, and
wherein the first active area is a PMOS region and the second active area is a NMOS region.

19. The method of claim 11 , further comprising:
forming a second trench isolation region that separates the logic cell from an adjacent logic cell; and
forming a second buried connection line, the second buried connection line is a power connection line connected to a power source.

20. The method of claim 11 , further comprising:
forming a second trench isolation region in the peripheral region,
wherein the signal connection line is for transmitting at least one of a data signal, a clock signal, or a command signal to the logic cell, and the first active area is a PMOS region and the second active area is a NMOS region,
wherein the second trench isolation region separates the logic cell from an adjacent logic cell and includes a second buried connection line that is a power connection line connected to a power source.

Assignees

• Micron Technology Inc

Inventors

• Lee Kyuseok
• Hwang Sangmin
• Kim Byung Yoon

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title