Reliable multi-information entropy physical unclonable function (PUF) for internet of things security

Patent metadata

Field	Value
Publication number	US-12063038-B2
Application number	US-202217900867-A
Country	US
Kind code	B2
Filing date	Sep 1, 2022
Priority date	Sep 15, 2021
Publication date	Aug 13, 2024
Grant date	Aug 13, 2024

Abstract

A reliable multi-information entropy PUF for Internet of Things security includes a control circuit, a data register, 128 glitch generation circuits, a 128-to-1 multiplexer, and a Schmidt glitch sampling module. The control circuit controls the data register to generate a square signal, the 128 glitch generation circuits to generate glitch signals to be output and the 128-to-1 multiplexer to select the glitch signals to be output. The Schmidt glitch sampling module samples the glitch signals to obtain PUF response outputs. Each glitch generation circuit generates a glitch signal by means of a fully symmetrical structure. The Schmidt glitch sampling module comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a buffer module and a D flip-flop.

First claim

What is claimed is:

1. A reliable multi-information entropy physical unclonable function (PUF) for Internet of Things security, comprising a control circuit, a data register, 128 glitch generation circuits, a 128-to-1 multiplexer, and a Schmidt glitch sampling module,
wherein the data register has an input terminal and an output terminal, each one of the 128 glitch generation circuits has an input terminal, an output terminal and a control terminal, the 128-to-1 multiplexer has 128 input terminals, a selection terminal and an output terminal, the Schmidt glitch sampling module has an input terminal and an output terminal,
wherein the control circuit is connected to the input terminal of the data register, the control terminal of each one of the 128 glitch generation circuits, and the selection terminal of the 128-to-1 multiplexer, wherein the output terminal of the data register is connected to the input terminals of the 128 glitch generation circuits, wherein the output terminals of the 128 glitch generation circuits are connected to the 128 input terminals of the 128-to-1 multiplexer in a one-to-one corresponding manner, wherein the output terminal of the 128-to-1 multiplexer is connected to the input terminal of the Schmidt glitch sampling module,
wherein the control circuit is used for controlling the data register to generate a square signal that is output via the output terminal of the data register to control the 128 glitch generation circuits to generate glitch signals to be output and to control the 128-to-1 multiplexer to select the glitch signals to be output, wherein the Schmidt glitch sampling module is used for sampling the glitch signals that is input to the Schmidt glitch sampling module to obtain a PUF response output, wherein each one of the 128 glitch generation circuits generates one of the glitch signals via a fully symmetrical structure,
wherein the Schmidt glitch sampling module comprises a first p-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first n-type metal-oxide-semiconductor (NMOS) transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a buffer module and a D flip-flop,
wherein the buffer module is formed by n buffers that are connected in series, n is an integer greater than or equal to 2, wherein an input terminal of a first buffer of the n buffers is an input terminal of the buffer module, an output terminal of a j th buffer of the n buffers is connected to an input terminal of a (j+1) th buffer of the n buffers, j is an integer which is in a range of 1 to n−1, wherein an output terminal of a n th buffer of the buffers is an output terminal of the buffer module, wherein the D flip-flop has a clock terminal, an input terminal and an output terminal,
wherein a power source is accessed to a source terminal of the first PMOS transistor, a source terminal of the fourth PMOS transistor and a drain terminal of the third NMOS transistor, wherein a drain terminal of the first PMOS transistor, a source terminal of the second PMOS transistor and a source terminal of the third PMOS transistor are connected, wherein a gate terminal of the first PMOS transistor, a gate terminal of the second PMOS transistor, a gate terminal of the first NMOS transistor and a gate terminal of the second NMOS transistor are connected to a first connecting terminal which is the input terminal of the Schmidt glitch sampling module, wherein a drain terminal of the second PMOS transistor, a drain terminal of the first NMOS transistor, a gate terminal of the third PMOS transistor, a gate terminal of the third NMOS transistor, a gate terminal of the fourth PMOS transistor and a gate terminal of the fourth NMOS transistor are connected, wherein a drain terminal of the third PMOS transistor is grounded, wherein a drain terminal of the fourth PMOS transistor, a drain terminal of the fourth NMOS transistor, the input terminal of the buffer module and the input terminal of the D flip-flop are connected, wherein a source terminal of the first NMOS transistor, a drain terminal of the second NMOS transistor and a source terminal of the third NMOS transistor are connected, a source terminal of the second NMOS transistor is grounded, wherein a source terminal of the fourth NMOS transistor is grounded, wherein the output terminal of the buffer module and the clock terminal of the D flip-flop are connected, and the output terminal of the D flip-flop is the output terminal of the Schmidt glitch sampling module.

2. The reliable multi-information entropy PUF for Internet of Things security according to claim 1 , wherein each glitch generation circuit of the 128 glitch generation circuits comprises four two-input OR gates that are identical in structure, four inverters that are identical in structure, two buffers that are identical in structure, two two-input AND gates that are identical in structure, a two-input XOR gate, and eight delay modules that identical in structure,
wherein each one of the four two-input OR gates has a first input terminal, a second input terminal and an output terminal, each one of the two two-input AND gates has a first input terminal, a second input terminal and an output terminal, the two-input XOR gate has a first input terminal, a second input terminal and an output terminal, and each one of the eight delay modules has an input terminal, an output terminal and a control terminal,
wherein the first input terminals and the second input terminals of the fourth two-input OR gates are connected to a second connecting terminal which is the input terminal of the glitch generation circuit,
wherein an output terminal of a first two-input OR gate of the four two-input OR gates is connected to an input terminal of a first inverter of the four inverters, an output terminal of a second two-input OR gate of the four two-input OR gates is connected to an input terminal of the first buffer, an output terminal of a third two-input OR gate of the four two-input OR gates is connected to an input terminal of a second inverter of the four inverters, an output terminal of a fourth two-input OR gate of the four two-input OR gates is connected to the input terminal of the second buffer,
wherein an output terminal of the first inverter is connected to an input terminal of a first delay module of the eight delay modules, an output terminal of the first buffer is connected to an input terminal of a second delay module of the eight delay modules, an output terminal of the second inverter is connected to an input terminal of a third delay module of the eight delay modules, the output terminal of the second buffer is connected to the input terminal of the fourth delay module of the eight delay modules,
wherein an output terminal of the first delay module is connected to a first input terminal of a first two-input AND gate of the two two-input AND gates, an output terminal of the second delay module is connected to a second input terminal of the first two-input AND gate, an output terminal of the third delay module is connected to a first input terminal of a second two-input AND gate of the two two-input AND gates, an output terminal of the fourth delay module of the eight delay modules is connected to a second input terminal of the second two-input AND gate, an output terminal of the first two-input AND gate is connected to an input terminal of the fifth delay module of the eight delay modules and an input terminal of the sixth delay module of the eight delay modules, an output terminal of the second two-input AND gate is connected to an input terminal of the seventh delay module of the eight delay modules and an input terminal of an eighth delay module of the eight delay modules,
wherein an output terminal of the fifth delay module and an output terminal of the sixth delay module are connect

Assignees

• Univ Wenzhou

Inventors

• Wang Pengjun
• Ni Li
• Zhou Di
• Zhang Yue Jun
• Chen Bo
• Guan Xiaochun

Classifications

• H03K19/1774

  for global signals, e.g. clock, reset · CPC title

• H03K19/1737 Primary

  using multiplexers (H03K19/1738 takes precedence) · CPC title

• H03K19/17768 Primary

  for security · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• H04L9/3278 Primary

  using physically unclonable functions [PUF] · CPC title