DC-DC converter apparatus with time-based control loop and corresponding control method, and computer program product

Patent metadata

Field	Value
Publication number	US-12062981-B2
Application number	US-202217569296-A
Country	US
Kind code	B2
Filing date	Jan 5, 2022
Priority date	Jan 7, 2021
Publication date	Aug 13, 2024
Grant date	Aug 13, 2024

Abstract

A time based boost DC-DC converter generates an output voltage using an inductor. A voltage error between the output voltage and a reference voltage is determined and processed in a) an integral control branch which converts the voltage error into an integral control current signal used to control a current controlled oscillator, and b) a proportional branch which converts the voltage error into a proportional control current signal used to control signal a delay line. Current flowing in the inductor is sensed, attenuated and used to apply adjustment to the integral and proportional control current signals. The output from the current controlled oscillator is passed through the delay line and phase detected in order to generate pulse width modulation (PWM) control signaling driving switch operation in the converter.

First claim

The invention claimed is:

1. A time-based boost DC-DC converter apparatus, comprising:
a DC-DC boost converter architecture including: a boost inductor arranged to receive an input voltage from a voltage generator, an output capacitor coupled to an output node in parallel with an output load, and a switching network configured to selectively couple the boost inductor to the output node under the control of a pulse width modulation (PWM) driving signal;
a time-based control loop coupled to the output node and configured to provide said PWM driving signal by performing a voltage to time conversion of a voltage error between an output voltage and a reference voltage and to generate said PWM driving signal on the basis of said voltage to time of conversion of the voltage error;
wherein said time-based control loop comprises:
an integral control branch configured to convert said voltage error into an integral control current signal used to generate a first control signal for controlling a current controlled oscillator that supplies a first signal having a frequency on which a switching frequency of the PWM driving signal depends, operating with a first phase depending on said integral control current signal; and
a proportional branch configured to convert said voltage error into a proportional control current signal used to generate a second control signal for controlling a delay line that receives said first signal operating with the first phase and sums in said first signal a second phase depending on said proportional control current signal to obtain a time signal;
a phase detector that receives said time signal and outputs a switching voltage having a duty cycle that depends on a detected phase of the time signal; and
a driver circuit that receives the switching voltage and controls the generation of said PWM driving signal driving the switching network of said DC-DC boost converter architecture;

wherein said converter apparatus is configured to obtain said first control signal for controlling said current controlled oscillator and said second control signal for controlling said delay line by taking a current flowing in the boost inductor and by, respectively:
multiplying said current flowing in the boost inductor by a first attenuation value to obtain a first compensation current which is summed to said proportional control current signal; and
multiplying said current flowing in the boost inductor by a second attenuation value to obtain a second compensation current which is summed to said integral control current signal;

said converter apparatus further configured to estimate a DC component of the current flowing in the boost inductor; and subtract said DC component of the current flowing in the boost inductor multiplied by the first attenuation value from the first compensation current signal and subtract said DC component of the current flowing in the boost inductor multiplied by the second attenuation value from the second compensation current signal.

2. The converter apparatus according to claim 1 , further configured to:
sum said current flowing in the boost inductor, multiplied by one of the first or second attenuation values, by injecting in a respective node of said proportional branch or integral branch to which said proportional control current signal or integral control current signal is brought; and
subtract said DC component multiplied by the first attenuation value or by the second attenuation value by injecting in a respective node to which said first compensation current signal or said second compensation current signal is brought.

3. The converter apparatus according to claim 1 , wherein said DC component is estimated on the basis of current flowing in the load divided by an efficiency of the converter apparatus and by one minus the duty cycle of the PWM driving signal.

4. The converter apparatus according to claim 1 , wherein said proportional branch comprises:
a first differential transconductance amplifier configured to convert the voltage error by multiplying said first current signal by a proportional transconductance value for output on a differential output of the first differential transconductance amplifier;
a first summing node configured to sum said DC component multiplied by the first attenuation value to one of the differential outputs; and
a second summing node configured to subtract said DC component multiplied by the first attenuation value from the other of the differential outputs.

5. The converter apparatus according to claim 4 , wherein said integral branch comprises:
a second differential transconductance amplifier configured to convert the voltage error by multiplying said second current signal by an integral transconductance value for output on a differential output of the second differential transconductance amplifier;
a third summing node configured to sum said DC component multiplied by the second attenuation value to one of the differential outputs; and
a fourth summing node configured to subtract said DC component multiplied by the second attenuation value from the other differential outputs.

6. The converter apparatus according to claim 5 , wherein said current controlled oscillator comprises first and second current controlled oscillators controlled by said integral differential outputs and configured to supply to first and second delay lines, respectively, controlled by said proportional different outputs, wherein the output signal of said first and second delay lines is applied to said phase detector which is configured to generate said switching voltage at said switching frequency and with a duty cycle proportional to the phase difference.

7. The converter apparatus according to claim 5 , wherein said current sensing circuit comprises:
first and second cascoded mirror arrangements having a common input coupled to receive a bias current from a current generator and having output branches coupled, respectively, to input and to output of a further current mirror, at which output is also formed an output signal of the sensing circuit, wherein terminals of said sense resistance are coupled, respectively, to output nodes of said first and second cascoded mirror arrangements, said load sensor further comprising a compensation transistor coupled to the output node of one of the cascaded mirror arrangements to supply a compensation current.

8. The converter apparatus according to claim 7 , wherein said load sensor includes a switching network, controlled by a control signal operating at the switching frequency with said duty cycle, that selectively couples said compensation arrangement to said output node.

9. The converter apparatus according to claim 8 , wherein said load sensor includes a bias current generator coupled to the output terminal of the first cascoded mirror arrangement to supply a further bias current and a further switching network driven by the same control signal operating at the switching frequency with said duty cycle driving said first switching network selectively coupling said bias current generator to said output terminal, so that the further bias current and the compensation current are coupled to said output terminal in the same time intervals.

10. The converter apparatus according to claim 1 , wherein said DC component is estimated on the basis of current flowing in the load divided by an efficiency of the converter apparatus and by one minus the duty cycle of the PWM driving signal of the converter apparatus, and wherein current flowing in the load is detected by a load sensor including a current sensing circuit comprising a sense resistance inserted in the path of the load current and applying a variable gain to the load current prop

Assignees

• St Microelectronics Srl

Inventors

• Gasparini Alessandro
• Bertolini Alessandro
• Leoncini Mauro
• Ghioni Massimo
• Levantino Salvatore

Classifications

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M1/0025 Primary

  Arrangements for modifying reference values, feedback values or error values in the control loop of a converter · CPC title

• H02M1/0009 Primary

  Devices or circuits for detecting current in a converter · CPC title

• H02M3/157

  with digital control · CPC title