Multi-zone radio frequency transistor amplifiers
US-11533024-B2 · Dec 20, 2022 · US
Epitaxies of a chemical compound semiconductor
US12062541B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12062541-B2 |
| Application number | US-202217873274-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 26, 2022 |
| Priority date | Mar 17, 2014 |
| Publication date | Aug 13, 2024 |
| Grant date | Aug 13, 2024 |
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- Title
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Abstract
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Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.
First claim
Opening claim text (preview).
What is claimed is: 1. A structure comprising: a substrate; a prelayer; a barrier layer including one of GaAs and InGaAs; and a channel layer; wherein the barrier layer is between the substrate and the channel layer and a concentration of dopant in the barrier layer is in an order of 10 17 cm −3 . 2. The structure of claim 1 , wherein the channel layer includes a pair of layers of common composition and an InAs layer between the pair of layers, the InAs layer of different composition than the pair of layers. 3. The structure of claim 1 , wherein the channel layer is disposed within a transistor. 4. The structure of claim 1 , wherein the barrier layer is P-type or N-type. 5. The structure of claim 1 , wherein the prelayer includes arsenic. 6. A structure comprising: a substrate; a prelayer formed at a graded temperature; a barrier layer; and a channel layer; wherein the barrier layer is between the substrate and the channel layer and a concentration of dopant in the barrier layer is in an order of 10 17 cm −3 . 7. The structure of claim 6 , wherein the channel layer includes a pair of layers of common composition and an InAs layer between the pair of layers, the InAs layer of different composition than the pair of layers. 8. The structure of claim 6 , wherein the channel layer includes AlSb. 9. The structure of claim 6 , wherein the channel layer includes AlGaSb. 10. The structure of claim 6 , wherein the channel layer includes AlInSb. 11. The structure of claim 6 , wherein the channel layer includes InAs. 12. A structure comprising: a substrate; a prelayer; a barrier layer; and a channel layer including a heterostructure comprising InAs; wherein the barrier layer is between the substrate and the channel layer and a concentration of dopant in the barrier layer is in an order of 10 17 cm −3 . 13. The structure of claim 12 , wherein the channel layer includes a pair of layers of common composition and an InAs layer between the pair of layers, the InAs layer of different composition than the pair of layers. 14. The structure of claim 12 , wherein heterostructure includes AlSb. 15. The structure of claim 12 , wherein heterostructure includes AlGaSb. 16. The structure of claim 12 , wherein heterostructure includes AlInSb. 17. The structure of claim 12 , wherein heterostructure includes InAs. 18. The structure of claim 12 , wherein the channel layer is disposed within a transistor. 19. The structure of claim 12 , wherein the barrier layer is P-type or N-type. 20. The structure of claim 12 , wherein the prelayer includes arsenic.
Assignees
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Classifications
Antimonides · CPC title
Arsenides · CPC title
Graded layers · CPC title
consisting of two layers · CPC title
Arsenides · CPC title
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Frequently asked questions
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- What does patent US12062541B2 cover?
- Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the cha…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg Co Ltd, Univ National Chiao Tung, Taiwan Semiconductor Manufacturing Company Limited & National Chiao Tung Univ
- What technology area does this patent fall under?
- Primary CPC classification H10P14/24. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 13 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).