Display panel and electronic device

US12062330B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12062330-B2
Application numberUS-202117610536-A
CountryUS
Kind codeB2
Filing dateSep 18, 2021
Priority dateSep 10, 2021
Publication dateAug 13, 2024
Grant dateAug 13, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure provides an electronic device and a display panel. The display panel includes a transition display region and a transparent display region. First pixel driving circuits are placed in the transition display region. Dummy pixel driving circuits are placed in the transition display region. One of the dummy pixel driving circuit is adjacently placed within a predetermined distance from at least one side of the first pixel driving circuits arranged along the second direction. This could reduce the environment difference between the pixel driving circuit close to the light sensing region and the pixel driving circuit inside the transition display region and thus reduce the luminance difference between the first display pixels controlled by the pixel driving circuit close to the light sensing region and the first display pixels controlled by the pixel driving circuit inside the transition display region.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel, having an additional function region that comprises a transition display region and a transparent display region, the transition display region placed in a peripheral region of the transparent display region, the display panel comprising: a plurality of display pixels, placed in the transition display region and the transparent display region; a plurality of first pixel driving circuits, placed in the transition display region, each of the plurality of first pixel driving circuits is electrically connected to at least one corresponding first display pixel of the plurality of display pixels; a plurality of dummy pixel driving circuits, placed in the transition display region; and a plurality of data lines, extending along the first direction and distributed along the second direction; wherein a part of the plurality of dummy pixel driving circuits located in a same column is electrically connected to a same data line, a column of the dummy pixel driving circuits and an adjacent column of the first pixel driving circuits are respectively electrically connected to two adjacent data lines; wherein the plurality of first pixel driving circuits extend along a first direction as columns, the columns of the first pixel driving circuits are arranged along a second direction, and the first direction and the second direction are different; wherein in each of the columns of the first pixel driving circuits, a first pixel driving circuit or a dummy pixel driving circuit is adjacently placed within a predetermined distance from at least one side of at least part of the first pixel driving circuits arranged along the second direction; wherein the plurality of dummy pixel driving circuits extend along the first direction as a column, at least one column of the dummy pixel driving circuits is adjacently placed within a predetermined distance from a side of at least two columns of a plurality of columns of first pixel driving circuits arranged along the second direction; wherein the transition display region has a plurality of pixel driving circuit islands arranged in an interval distribution, each of the pixel driving circuit islands comprises multiple first pixel driving circuits; wherein a distance between two adjacent pixel driving circuit islands is greater than the predetermined distance, a corresponding column of the dummy pixel driving circuits is placed at one side edge of a pixel driving circuit island along the second direction, where the side edge of the pixel driving circuit island along the second direction is closer to its adjacent pixel driving circuit; wherein a column of the first pixel driving circuits in the pixel driving circuit island closest to its adjacent pixel driving circuit and a corresponding dummy pixel driving circuit are respectively electrically connected to two adjacent data lines. 2. The display panel of claim 1 , wherein the transition display region has m first pixel driving circuits and m data lines, an n th column of the first pixel driving circuits is electrically connected to an n th data line; wherein a column of the dummy pixel driving circuits is placed within a predetermined distance from one side of the n th column of the first pixel driving circuits, the dummy pixel driving circuits are electrically connected to a data line other than the n th data line, wherein n is greater than or equal to 1 and is smaller than or equal to m. 3. The display panel of claim 2 , wherein the plurality of dummy pixel driving circuits comprises a first dummy pixel driving circuit and a second dummy pixel driving circuit; wherein a column of the first dummy pixel driving circuit is placed at a side of the n th column of the first pixel driving circuit close to an (n+1) th column of the first pixel driving circuits, the first dummy pixel driving circuit is electrically connected to an a th data line; wherein a column of the second dummy pixel driving circuit is placed at a side of the (n+1) th column of the first pixel driving circuit close to the n th column of the first pixel driving circuit, the second dummy pixel driving circuit is electrically connected to a b th data line; and wherein n is greater than or equal to (m−1), a is greater than or equal to (n+1) and b is smaller than or equal to n. 4. The display panel of claim 3 , wherein each column of the first and second dummy pixel driving circuits and its adjacent column of the first pixel driving circuits are respectively electrically connected to adjacent data lines, wherein a is equal to (n+1) and b is equal to n. 5. The display panel of claim 2 , wherein the plurality of dummy pixel driving circuit comprises a first dummy pixel driving circuit and a second dummy pixel driving circuit; wherein a column of the first dummy pixel driving circuits is placed at a side of the n th column of the first pixel driving circuit close to an (n+1) th column of the first pixel driving circuit, the first dummy pixel driving circuit is electrically connected to an a th data line; wherein a column of the second dummy pixel driving circuit is placed at a side of the (n+1) th column of the first pixel driving circuit close to the n th column of the first pixel driving circuit, the second dummy pixel driving circuit is electrically connected to a b th data line; and wherein n is greater than or equal to (m−1), a is smaller than or equal to (n−1) and b is greater than or equal to (n+2). 6. The display panel of claim 5 , wherein each column of the first and second dummy pixel driving circuits and its adjacent column of the first pixel driving circuits are respectively electrically connected to adjacent data lines, wherein a is equal to (n−1) and b is equal to (n+2). 7. The display panel of claim 1 , wherein each of the first pixel driving circuits is electrically connected to a plurality of the first display pixels. 8. The display panel of claim 1 , wherein along the second direction, a corresponding column of the dummy driving circuits is placed between a column of the first pixel driving circuits in the transition display region closest to the transparent display region and the transparent display region; wherein a column of the first pixel driving circuits in the transition display region closest to the transparent display region and a corresponding column of the dummy pixel driving circuits are respectively electrically connected to two adjacent data lines. 9. The display panel of claim 8 , wherein along the second direction, a column of the dummy pixel driving circuits placed at one side of the transparent display region is electrically connected to a data line corresponding to a column of the first pixel driving circuits placed at another side of the transparent display region. 10. The display panel of claim 9 , along the second direction, a column of the dummy pixel driving circuits placed at one side of the transparent display region is electrically connected to a data line corresponding to a column of the first pixel driving circuits placed at another side of the transparent display region closest to the transparent display region. 11. The display panel of claim 10 , wherein the first pixel driving circuits and the first display pixels are one-by-one electrically connected to each other. 12. The display panel of claim 1 , wherein the display panel has a main display region placed in a peripheral region of the additional function region, and the display panel further comprises: a plurality of second display pixels, placed in the main display region; and a plurality of second pixel driving circuits, placed in the main display region, the second pixel driving ci

Assignees

Inventors

Classifications

  • Improving the luminance or brightness uniformity across the screen · CPC title

  • Details of dummy pixels or dummy lines in flat panels · CPC title

  • Dummy elements, i.e. elements having non-functional features · CPC title

  • Interconnections, e.g. wiring lines or terminals · CPC title

  • Connection of the pixel electrodes to the thin film transistors [TFT] · CPC title

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Frequently asked questions

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What does patent US12062330B2 cover?
The present disclosure provides an electronic device and a display panel. The display panel includes a transition display region and a transparent display region. First pixel driving circuits are placed in the transition display region. Dummy pixel driving circuits are placed in the transition display region. One of the dummy pixel driving circuit is adjacently placed within a predetermined dis…
Who is the assignee on this patent?
Wuhan China Star Optoelectronics Semiconductor Display Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3208. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 13 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).