Display panel and display device

Patent metadata

Field	Value
Publication number	US-12062248-B2
Application number	US-202118009220-A
Country	US
Kind code	B2
Filing date	May 25, 2021
Priority date	Jun 9, 2020
Publication date	Aug 13, 2024
Grant date	Aug 13, 2024

Abstract

A display panel and a display device are provided. The display panel has a touch side and includes an array substrate and an opposite substrate arranged opposite to each other. The array substrate includes an image sensor array including a plurality of image sensors each including a photosensitive element configured to receive light reflected by a texture touched on the touch side for texture acquisition; the opposite substrate includes a light shielding layer including a plurality of first openings arranged in an array, and the plurality of first openings are in one-to-one correspondence with and partially overlap with the photosensitive elements of the plurality of image sensors in a direction perpendicular to a panel surface of the display panel.

First claim

What is claimed is:

1. A display panel having a touch side and comprising an array substrate and an opposite substrate arranged opposite to each other,
wherein the array substrate comprises an image sensor array comprising a plurality of image sensors, and each of the plurality of image sensors comprises a photosensitive element configured to receive light reflected by a texture touched on the touch side for texture acquisition; and
the opposite substrate comprises a light shielding layer comprising a plurality of first openings arranged in an array, and the plurality of first openings are in one-to-one correspondence with and at least partially overlap with the photosensitive elements of the plurality of image sensors in a direction perpendicular to a panel surface of the display panel;
wherein for one first opening and one image sensor that are correspondingly arranged, an orthographic projection of the first opening on the panel surface of the display panel is inside an orthographic projection of the photosensitive element of the image sensor on the panel surface of the display panel; and
wherein for one first opening and one image sensor that are correspondingly arranged, a distance between an edge of the orthographic projection of the first opening on the panel surface of the display panel and an edge of the orthographic projection of the photosensitive element of the image sensor on the panel surface of the display panel is 0 μm to 5 μm.

2. The display panel according to claim 1 , wherein the array substrate further comprises a plurality of sub-pixels arranged in an array,
the light shielding layer further comprises a plurality of second openings arranged in an array and a plurality of color filters respectively arranged in the plurality of second openings, and
the plurality of color filters are in one-to-one correspondence with and at least partially overlap with the plurality of sub-pixels in the direction perpendicular to the panel surface of the display panel.

3. The display panel according to claim 2 , wherein each of the plurality of image sensors further comprises at least one switching element,
the photosensitive element comprises a first electrode, a second electrode and a semiconductor layer between the first electrode and the second electrode, wherein the first electrode is electrically connected with the at least one switching element through a first via hole, and
the semiconductor layer partially overlaps with or has no overlap with the first via hole in the direction perpendicular to the panel surface of the display panel.

4. The display panel according to claim 3 , wherein the array substrate further comprises a base substrate and a first planarization layer, wherein,
the at least one switching element is arranged on the base substrate, and the at least one switching element comprises a switching transistor, the switching transistor comprises an active layer, a gate electrode and a source-drain electrode; the first planarization layer is arranged at a side of the switching transistor away from the base substrate to provide a flat surface; the first electrode is arranged at a side of the first planarization layer away from the base substrate; the first planarization layer has the first via hole; and the first electrode is electrically connected with the source-drain electrode through the first via hole.

5. The display panel according to claim 4 , wherein each of the plurality of sub-pixels comprises a pixel driving circuit, the pixel driving circuit is arranged on the base substrate and comprises a thin film transistor, and the thin film transistor is arranged in a same layer as the switching transistor.

6. The display panel according to claim 5 , wherein the array substrate further comprises a first connection electrode, a second planarization layer, a second connection electrode and a connection trace, wherein
the first planarization layer also has a second via hole, the first connection electrode is electrically connected with a source-drain electrode of the thin film transistor through the second via hole, and the first connection electrode and the first electrode are arranged in a same layer;
the semiconductor layer and the second electrode are sequentially arranged on the first electrode;
the second planarization layer is arranged at a side of the first connection electrode and the second electrode away from the base substrate, the second planarization layer has a third via hole and a fourth via hole, the second connection electrode is electrically connected with the first connection electrode through the third via hole, the connection trace is electrically connected with the second electrode through the fourth via hole, and the connection trace is arranged in a same layer as the second connection electrode.

7. The display panel according to claim 6 , wherein the array substrate further comprises a third planarization layer and a pixel electrode, wherein
the third planarization layer is arranged at a side of the second connection electrode and the connection trace away from the base substrate, and the third planarization layer has a fifth via hole through which the pixel electrode is electrically connected with the second connection electrode.

8. The display panel according to claim 7 , further comprising a common electrode, wherein
the common electrode is arranged on the array substrate and insulated from the pixel electrode through an insulating layer; or
the common electrode is arranged on the opposite substrate.

9. The display panel according to claim 3 , wherein the at least one switching element comprises a first switching transistor, a second switching transistor and a third switching transistor, the first electrode is electrically connected with a source-drain electrode of the third switching transistor through the first via hole, the first electrode is also electrically connected with a gate electrode of the second switching transistor, and a source-drain electrode of the second switching transistor is electrically connected with a source-drain electrode of the first switching transistor.

10. The display panel according to claim 2 , wherein the plurality of sub-pixels are arranged in an array of multiple rows and multiple columns,
the display panel also comprises a scanning line extending between two adjacent rows of sub-pixels, and the scanning line is configured to provide a scanning signal for the plurality of sub-pixels,
at least some of the plurality of image sensors are arranged between two adjacent rows of sub-pixels, and an extending direction of the photosensitive elements of the at least some of the plurality of image sensors is as same as an extending direction of the scanning line.

11. The display panel according to claim 10 , wherein the photosensitive elements of the at least some of the plurality of image sensors have no overlap with the scanning line in the direction perpendicular to the panel surface of the display panel.

12. The display panel according to claim 1 , wherein a planer shape of each of the plurality of first openings is square or rectangular shape, and a length×a width of the planer shape is 10 μm×10 μm to 50 μm×50 μm.

13. The display panel according to claim 1 , further comprising a liquid crystal layer between the array substrate and the opposite substrate,
wherein the display panel is configured to control the liquid crystal layer in response to a control signal so that a first area is in a light-transmitting state.

14. A display device, comprising:
the display panel according to claim 1 , and
a backlight assembly arranged at a side of the array substr

Assignees

• Boe Technology Group Co Ltd

Inventors

• Li Changfeng
• Chen Xiaochuan
• Li Fuqiang
• Liu Liwei
• Wang Hongrun
• Zhang Hui
• Zhang Shunhang
• Hou Kai
• Im Yunsik
• Di Yunping

Classifications

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/136209

  Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

• G02F1/136222

  Colour filters incorporated in the active matrix substrate · CPC title

• G06V40/1318 Primary

  using electro-optical elements or layers, e.g. electroluminescent sensing · CPC title