Arithmetic logic unit, multiply-accumulate operation device, multiply-accumulate operation system, and multiply-accumulate operation method

Patent metadata

Field	Value
Publication number	US-12061877-B2
Application number	US-201917258965-A
Country	US
Kind code	B2
Filing date	Jul 12, 2019
Priority date	Jul 17, 2018
Publication date	Aug 13, 2024
Grant date	Aug 13, 2024

Abstract

An arithmetic logic unit according to an embodiment of the present technology includes: a plurality of input lines; and a multiply-accumulate operation device. Pulse signals corresponding to input values are input to the plurality of input lines. The multiply-accumulate operation device includes a plurality of multiplication units that generates, on the basis of the pulse signals input to each of the plurality of input lines, charges corresponding to multiplication values obtained by multiplying the input values by weight values, and an output unit that outputs a multiply-accumulate signal representing a sum of the multiplication values by accumulating the charges corresponding to the multiplication values generated by each of the plurality of multiplication units. A value of at least one of the input value or the weight value is limited.

First claim

The invention claimed is:

1. An arithmetic logic unit, comprising:
a plurality of input lines, pulse signals corresponding to each of a plurality of input values being input to the plurality of input lines; and
a multiply-accumulate operation device that includes
a plurality of multiplication circuits that respectively generate, on a basis of the pulse signals input to each of the plurality of input lines, charges corresponding to multiplication values obtained by multiplying a respective input value by a respective weight value, and
an output circuit that outputs a multiply-accumulate signal representing a sum of the multiplication values by accumulating the charges corresponding to the multiplication values generated by each of the plurality of multiplication circuits, wherein

a value of at least one of the respective input value or the respective weight value is limited.

2. The arithmetic logic unit according to claim 1 , wherein
the value of the at least one of the respective input value or the respective weight value is limited to fall within a predetermined value range.

3. The arithmetic logic unit according to claim 2 , wherein
the predetermined value range includes a plurality of limit values, and
the value of the at least one of the respective input value or the respective weight value is set to one of the plurality of limit values.

4. The arithmetic logic unit according to claim 3 , wherein
the plurality of limit values includes zero.

5. The arithmetic logic unit according to claim 3 , wherein
the plurality of limit values includes a positive limit value and a negative limit value that have absolute values equal to each other.

6. The arithmetic logic unit according to claim 1 , wherein
the respective weight value is limited by first processing of setting the respective weight value on a basis of a first value that is an absolute value of a value to be the respective weight value.

7. The arithmetic logic unit according to claim 6 , wherein
when the first value is a first threshold value or less, the respective weight value is set to zero.

8. The arithmetic logic unit according to claim 6 , wherein
the respective weight value is set to zero at a first ratio in order from the smallest first value, each respective weight value being set for each of the plurality of multiplication circuits.

9. The arithmetic logic unit according to claim 1 , wherein
the respective input value is limited by second processing of setting the respective input value on a basis of a second value that is an absolute value of a value to be the respective input value.

10. The arithmetic logic unit according to claim 9 , wherein
when the second value is a second threshold value or less, the respective input value is set to zero.

11. The arithmetic logic unit according to claim 9 , wherein
the respective input value is set to zero at a second ratio in order from the smallest second value, each respective input value being represented by a respective pulse signal input to each of the plurality of multiplication circuits.

12. The arithmetic logic unit according to claim 9 , further comprising
a limiting circuit that executes, using an absolute value of the sum of the multiplication values represented by the multiply-accumulate signal as the second value, the second limitation processing on a basis of the multiply-accumulate signal.

13. The arithmetic logic unit according to claim 1 , wherein
the pulse signal is input to each of the plurality of input lines within a predetermined input period, and
the output circuit outputs a multiply-accumulate signal representing the sum of the multiplication values within a predetermined output period.

14. The arithmetic logic unit according to claim 1 , wherein
the respective input value is a value represented by a first input value and a second input value, and
the plurality of input lines includes a plurality of pairs of the input lines, each of the pairs including a first input line and a second input line, a first pulse signal representing the first input value being input to the first input line, a second pulse signal representing the second input value being input to the second input line.

15. The arithmetic logic unit according to claim 1 , wherein
the pulse signal is a signal representing the respective input value using at least one of timing of a pulse or a pulse width.

16. A multiply-accumulate operation device, comprising:
a plurality of multiplication circuits that respectively generates, on a basis of the pulse signals input to each of a plurality of input lines, charges corresponding to multiplication values obtained by multiplying a respective input value by a respective weight value; and
an output circuit that outputs a multiply-accumulate signal representing a sum of the multiplication values by accumulating the charges corresponding to the multiplication values generated by each of the plurality of multiplication circuits, wherein
a value of at least one of the respective input value or the respective weight value is limited.

17. A multiply-accumulate operation system, comprising:
a plurality of input lines, pulse signals corresponding to input values being input to the plurality of input lines;
a plurality of multiply-accumulate operation devices that includes
a plurality of multiplication circuits that respectively generates, on a basis of the pulse signals input to each of the plurality of input lines, charges corresponding to multiplication values obtained by multiplying a respective input value by a respective weight value, and
an output circuit that outputs a multiply-accumulate signal representing a sum of the multiplication values by accumulating the charges corresponding to the multiplication values generated by each of the plurality of multiplication circuits; and

a network circuit configured by connecting the plurality of multiply-accumulate operation devices, wherein
a value of at least one of the respective input value or the respective weight value is limited.

18. A multiply-accumulate operation method, comprising:
inputting pulse signals corresponding to input values to a plurality of input lines;
generating, on a basis of the pulse signals input to each of the plurality of input lines, charges corresponding to multiplication values obtained by multiplying a respective input value by a respective weight value;
outputting a multiply-accumulate signal representing a sum of the multiplication values by accumulating the charges corresponding to the multiplication values; and
limiting a value of at least one of the respective input value or the respective weight value.

19. An arithmetic logic unit, comprising:
a plurality of input lines, pulse signals corresponding to input values being input to the plurality of input lines;
a multiply-accumulate operation device that includes
a plurality of multiplication circuits that respectively generates, on a basis of the pulse signals input to each of the plurality of input lines, charges corresponding to multiplication values obtained by multiplying a respective input value by a respective weight value, and
an output circuit that outputs a multiply-accumulate signal representing a sum of the multiplication values by accumulating the charges corresponding to the multiplication values generated by each of the plurality of multiplication circuits; and

a limitation processing circuit that limits a value of at least one of the respective input value or the respective weight value before each o

Assignees

• Sony Group Corp

Inventors

• Morie Takashi
• TAMUKOH Hakaru
• Wang Quan
• Fujinami Yasushi

Classifications

• G06F7/60

  Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations {, e.g. using difunction pulse trains, STEELE computers, phase computers (conversion of digital data to or from non-denominational form H03M5/00, H03M7/00)} · CPC title

• G06G7/60

  for living beings, e.g. their nervous systems {; for problems in the medical field} · CPC title

• G06N3/063

  using electronic means · CPC title

• G06F7/5443 Primary

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title