Storage device and operating method of storage device
US-10504566-B2 · Dec 10, 2019 · US
US12061816B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12061816-B2 |
| Application number | US-202218086770-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 22, 2022 |
| Priority date | Aug 11, 2020 |
| Publication date | Aug 13, 2024 |
| Grant date | Aug 13, 2024 |
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A storage system performing an overwrite, a host system controlling the storage system, and an operating method of the storage system, wherein the storage system includes a memory device; and a controller that receives new data and an overwrite request from the host system, wherein the overwrite request includes a first logical address for old data and a second logical address for the new data, and performs an overwrite operation by writing the new data corresponding to the second logical address to the memory device and invalidating the old data corresponding to the first logical address according to the overwrite request.
Opening claim text (preview).
What is claimed is: 1. A storage device comprising: a nonvolatile memory; a volatile memory; and a controller coupled to the nonvolatile memory and the volatile memory, and configured to receive first data and an overwrite request, wherein, in response to the overwrite request, the controller is configured to perform an overwrite operation by simultaneously writing the first data to a memory cell of the nonvolatile memory and invalidating second data stored in the memory cell of the nonvolatile memory, the controller is configured to store metadata for the first data and the second data to the volatile memory, the metadata including mapping information between logical addresses and physical addresses for the first data and the second data, and the controller is configured to update the metadata when the first data is written to the nonvolatile memory and the second data stored in the nonvolatile memory is invalidated. 2. The storage device of claim 1 , wherein the overwrite request includes a first logical address for the first data and a second logical address for the second data, and the second logical address is different from the first logical address. 3. The storage device of claim 1 , wherein the controller updates the metadata by adding the mapping information between a first logical address and a first physical address for the first data and invalidating the mapping information between a second logical address and a second physical address for the second data. 4. The storage device of claim 1 , wherein the storage device is a solid state drive (SSD). 5. The storage device of claim 1 , wherein the overwrite request includes a field value indicating a write command type. 6. The storage device of claim 1 , wherein the overwrite operation is performed by writing the first data to the same location where the second data is stored. 7. The storage device of claim 6 , wherein the first data is written simultaneously with an erasure of the second data. 8. The storage device of claim 1 , wherein the nonvolatile memory is a universal flash storage (UFS) memory. 9. A storage device comprising: a nonvolatile memory; a volatile memory; and a controller coupled to the nonvolatile memory and the volatile memory, and configured to receive first data and an overwrite request, wherein, in response to the overwrite request, the controller is configured to perform an overwrite operation by simultaneously writing the first data to a memory cell of the nonvolatile memory and erasing second data stored in the memory cell of the nonvolatile memory, and the controller is configured to store metadata for the first data and the second data to the volatile memory, the metadata including mapping information between logical addresses and physical addresses for the first data and the second data. 10. The storage device of claim 9 , wherein the controller updates the metadata when the first data is written to the nonvolatile memory and the second data stored in the nonvolatile memory is invalidated. 11. The storage device of claim 9 , wherein the first data is written to the same location where the second data is stored. 12. The storage device of claim 9 , wherein the storage device is a solid state drive (SSD). 13. The storage device of claim 9 , wherein the nonvolatile memory is a universal flash storage (UFS) memory. 14. The storage device of claim 9 , wherein the controller updates the metadata by adding the mapping information between a first logical address and a first physical address for the first data and invalidating the mapping information between a second logical address and a second physical address for the second data. 15. A storage device comprising: a nonvolatile memory; a volatile memory; and a controller coupled to the nonvolatile memory and the volatile memory, and configured to receive first data and an overwrite request, wherein, in response to the overwrite request, the controller is configured to perform an overwrite operation by simultaneously writing the first data to a memory cell of the nonvolatile memory and invalidating second data stored in the memory cell of the nonvolatile memory, the first data is written to the same location where the second data is stored, and the controller is configured to store metadata for the first data and the second data to the volatile memory, the metadata including mapping information between logical addresses and physical addresses for the first data and the second data. 16. The storage device of claim 15 , wherein the first data is written simultaneously with an erasure of the second data. 17. The storage device of claim 15 , wherein the controller updates the metadata when the first data is written to the nonvolatile memory and the second data stored in the nonvolatile memory is invalidated. 18. The storage device of claim 15 , wherein the storage device is a solid state drive (SSD). 19. The storage device of claim 15 , wherein the nonvolatile memory is a universal flash storage (UFS) memory.
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using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title
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