System with increasing protected storage area and erase protection

Patent metadata

Field	Value
Publication number	US-12061803-B2
Application number	US-202117499167-A
Country	US
Kind code	B2
Filing date	Oct 12, 2021
Priority date	Oct 14, 2020
Publication date	Aug 13, 2024
Grant date	Aug 13, 2024

Abstract

An apparatus may include a processor. The apparatus may include a memory communicatively coupled to the processor. The apparatus may include a memory control circuit (MCC). The MCC may be configured to define a protected portion of the memory, wherein the protected portion of the memory is configured for read-only access by the processor, increase a size of the protected portion of the memory, and, after the increase in size of the protected portion of the memory, prevent decreases of the size of the protected portion of the memory.

First claim

What is claimed is:

1. A method, comprising:
defining a protected portion as a subset of a memory block, the memory block including a contiguous set of memory addresses and communicatively coupled to a processor, wherein the protected portion of the memory block is configured for read-only access by the processor and the protected portion of the first memory block is a less than an entirety of the first memory block, wherein the read-only access includes a bulk erase setting and a self-write setting, the bulk erase setting of a higher precedence over the bulk erase setting;
increasing a size of the protected portion as the subset of the memory block;
after the increase in size of the protected portion as the subset of the memory block, preventing decreases of the size of the protected portion as the subset of the memory block;
in response to a determination that a bulk erase operation is allowed based on a first value stored in a first register, determining whether a self-write operation is allowed based on a second value stored in a second register; and
in response to a determination that the bulk erase operation is not allowed based on the first value stored in the first register, determining that the self-write operation is not allowed regardless of the second value stored in the second register.

2. The method of claim 1 , comprising permanently preventing decreasing the size of the protected portion as the subset of the memory block.

3. The method of claim 1 , comprising permanently increasing the size of the protected portion as the subset of the memory block.

4. The method of claim 1 , comprising, in order to increase the size of the protected portion as the subset of the memory block, writing a value to a fuse of the designation of address ranges of the protected portion as the subset of the memory block, the value to change a default value.

5. The method of claim 4 , comprising writing the value to the fuse of the designation of address ranges of the protected portion as the subset of the memory block based on a setting to designate a type of read-only behavior, the type of read-only behavior is a single type among a plurality of possible read-only behaviors.

6. The method of claim 5 , wherein the setting is to indicate that a bulk erase is not allowed, the bulk erase to include a command to completely erase one or more memory regions.

7. The method of claim 5 , comprising, based on the setting, preventing changes to the setting.

8. The method of claim 5 , comprising, based on the setting, preventing writes to the protected portion as the subset of the memory block.

9. The method of claim 1 , wherein the protected portion as the subset of the memory block is configured for read-only access by the processor through an indication that self write operations are not allowed.

10. The method of claim 1 , wherein the protected portion as the subset of the memory block is configured for protection access by the processor through an indication that read operations from a given memory address are not allowed.

11. An apparatus, comprising:
a processor;
a memory communicatively coupled to the processor, the memory including a plurality of memory blocks, the memory blocks including a contiguous set of memory addresses; and
a memory control circuit (MCC) to:
define a protected portion as a subset of a first memory block of the plurality of memory blocks, wherein the protected portion as the subset of the first memory block is configured for read-only access by the processor and the protected portion of the first memory block is less than an entirety of the first memory block;
increase a size of the protected portion as the subset of the first memory block;
after the increase in size of the protected portion as the subset of the first memory block, prevent decreases of the size of the protected portion as the subset of the first memory block;
in response to a determination that a bulk erase operation is allowed based on a first value stored in a first register, determine whether a self-write operation is allowed based on a second value stored in a second register; and
in response to a determination that the bulk erase operation is not allowed based on the first value stored in the first register, determine that the self-write operation is not allowed regardless of the second value stored in the second register.

12. The apparatus of claim 11 , wherein the MCC is to permanently prevent decrease of the size of the protected portion as the subset of the first memory block.

13. The apparatus of claim 11 , wherein the MCC is to permanently increase the size of the protected portion as the subset of the first memory block.

14. The apparatus of claim 11 , wherein the MCC is to, in order to increase the size of the protected portion as the subset of the first memory block, write a value to a fuse of a designation of address ranges of the protected portion as the subset of the first memory block, the value to change a default value.

15. The apparatus of claim 14 , wherein the MCC is to write the value to the fuse of the designation of address ranges of the protected portion as the subset of the first memory block based on a setting to designate a type of read-only behavior, the type of read-only behavior is a single type among a plurality of possible read-only behaviors.

16. The apparatus of claim 15 , wherein the setting is to configure the protected portion as the subset of the first memory block for read-only access through an indication that a bulk erase is not allowed, the bulk erase to include a command to completely erase one or more memory regions.

17. The apparatus of claim 15 , wherein the MCC is to, based on the setting, prevent changes to the setting.

18. The apparatus of claim 15 , wherein the MCC is to, based on the setting, prevent writes to the protected portion as the subset of the first memory block.

19. The apparatus of claim 11 , wherein the protected portion as the subset of the first memory block is configured for read-only access by the processor through an indication that self write operations are not allowed.

20. The apparatus of claim 11 , wherein the protected portion as the subset of the first memory block is configured for protection by the processor through an indication that read operations from a given memory address are not allowed.

Assignees

• Microchip Tech Inc

Inventors

• Samuel Roshan
• Pfeifer Erick
• Day John
• Ujvari Daniel

Classifications

• G06F3/0652

  Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title