Display device with signal line overlapping gate driving circuit

Patent metadata

Field	Value
Publication number	US-12058909-B2
Application number	US-202117517394-A
Country	US
Kind code	B2
Filing date	Nov 2, 2021
Priority date	Dec 4, 2020
Publication date	Aug 6, 2024
Grant date	Aug 6, 2024

Abstract

Embodiments of the present disclosure are related to a display device, as disposing a clock signal line on an area overlapping with an area where a gate circuit is disposed on a non-active area of a display panel, a gate driving circuit can be disposed on the non-active area while minimizing an increase of the non-active area. Furthermore, as disposing the clock signal line by using metal layers that a first metal layer with a low resistance and a second metal layer with a high reflectance are stacked, the clock signal line disposed on the non-active area and a pixel electrode disposed on an active area can be implemented as a same layer, the clock signal line disposed on the gate circuit can be implemented while reducing the number of masks.

First claim

What is claimed is:

1. A display device, comprising:
a plurality of pixel electrodes located in a plurality of subpixels disposed in an active area;
a gate driving circuit disposed in a non-active area located outside of the active area, and configured to output a scan signal to the plurality of subpixels, the gate driving circuit including an active layer, a gate electrode disposed above the active layer, and a source electrode and a drain electrode both disposed above the active layer; and
at least one signal line disposed in the non-active area, and disposed directly above and contacting a same layer either as a layer directly above which the plurality of pixel electrodes are disposed and contact, or as a layer directly above which a connection pattern electrically connected to one of the pixel electrodes is disposed and contacts,
wherein the at least one signal line is configured to supply a signal to one of the source and drain electrodes of the gate driving circuit.

2. The display device of claim 1 , wherein the at least one signal line is located above the gate driving circuit, and at least a portion of the at least one signal line is located above an area overlapping with the gate driving circuit.

3. The display device of claim 1 , wherein the at least one signal line is made of a same material as the plurality of pixel electrodes.

4. The display device of claim 1 , wherein each of the at least one signal line and the plurality of pixel electrodes comprises two or more metal layers.

5. The display device of claim 1 , wherein the at least one signal line comprises:
a first metal layer having a first resistance and a first reflectance; and
a second metal layer disposed above the first metal layer, having a second resistance greater than the first resistance, and having a second reflectance greater than the first reflectance.

6. The display device of claim 5 , wherein an area where the first metal layer is disposed and an area where the second metal layer is disposed are the same.

7. The display device of claim 5 , wherein the first metal layer comprises a hydrogen capture material.

8. The display device of claim 1 , further comprising:
a planarization layer located under the at least one signal line.

9. The display device of claim 8 , wherein the at least one signal line is electrically connected to at least one of a plurality of thin film transistors included in the gate driving circuit through a contact hole included in the planarization layer.

10. The display device of claim 8 , wherein each of the plurality of pixel electrodes is electrically connected to at least one thin film transistor included in each of the plurality of subpixels through a contact hole included in the planarization layer.

11. The display device of claim 1 , further comprising:
a bank layer located above an upper surface of the at least one signal line, and disposed in an area including an area overlapping with the at least one signal line.

12. The display device of claim 1 , wherein the at least one signal line includes at least one of a clock signal line, a gate high voltage line, and a gate low voltage line.

13. A display device, comprising:
a plurality of subpixels disposed in an active area, and configured to display an image;
a plurality of gate lines disposed in the active area and configured to supply a scan signal to the plurality of subpixels;
a gate driving circuit disposed in a non-active area located outside of the active area, and configured to output the scan signal to the plurality of gate lines, the gate driving circuit including an active layer, a gate electrode disposed above the active layer, and a source electrode and a drain electrode both disposed above the active layer; and
at least one signal line disposed in the non-active area, and located above and overlapping the source and drain electrodes of the gate driving circuit,
wherein the at least one signal line is configured to supply a signal to the gate driving circuit.

14. The display device of claim 13 , wherein the at least one signal line comprises:
a first metal layer; and
a second metal layer disposed above an area overlapping with the first metal layer above the first metal layer,
wherein at least one of a resistance and a reflectance of the second metal layer is different from at least one of a resistance and a reflectance of the first metal layer.

15. The display device of claim 13 , wherein the at least one signal line is disposed above a same layer as a layer where a pixel electrode located in each of a plurality of subpixels disposed in the active area is disposed.

16. The display device of claim 13 , further comprising:
a planarization layer located between the gate driving circuit and the at least one signal line; and
a bank layer located above an upper surface of the at least one signal line.

17. The display device of claim 16 , wherein the at least one signal line is electrically connected to at least one thin film transistor included in the gate driving circuit through a contact hole included in the planarization layer.

18. The display device of claim 17 , wherein at least a portion of the at least one signal line overlaps an active layer of the at least one thin film transistor.

19. The display device of claim 13 , wherein the plurality of gate lines are disposed above a different layer from a layer where the at least one signal line is disposed.

20. The display device of claim 13 , wherein the at least one signal line includes at least one of a clock signal line, a gate high voltage line, and a gate low voltage line.

21. A display device, comprising:
a display panel where a plurality of gate lines, a plurality of data lines and a plurality of subpixels are disposed;
a gate driving circuit disposed in a non-active area, and configured to output a scan signal to the plurality of gate lines, the gate driving circuit including an active layer, a gate electrode disposed above the active layer, and a source electrode and a drain electrode both disposed above the active layer;
a planarization layer covering the source and drain electrodes of the gate driving circuit;
at least one signal line disposed in the non-active area, located above and overlapping the source and drain electrodes of the gate driving circuit, and configured to supply a signal to the gate driving circuit; and
a plurality of pixel electrodes located in the plurality of subpixels,
wherein the at least one signal line and one of the plurality of pixel electrodes are disposed directly above and contact the planarization layer, and
wherein the plurality of pixel electrodes comprise a first metal layer having a first reflectance and a second metal layer located above the first metal layer and having a second reflectance greater than the first reflectance.

22. The display device of claim 21 , wherein the at least one signal line includes same first and second metal layers as the first and second metal layers of the plurality of pixel electrodes.

23. The display device of claim 21 , wherein the at least one signal line includes at least one of a clock signal line, a gate high voltage line, and a gate low voltage line.

Assignees

• Lg Display Co Ltd

Inventors

• Youn Jae-Woong
• Son Kiwon
• Park Minseon

Classifications

• H10K59/122

  Pixel-defining structures or layers, e.g. banks · CPC title

• G09G3/3225

  using an active matrix · CPC title

• G09G2310/0264

  Details of driving circuits · CPC title

• H10K50/818

  Reflective anodes, e.g. ITO combined with thick metallic layers · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title