Display device that alleviates limitations in materials

Patent metadata

Field	Value
Publication number	US-12058891-B2
Application number	US-201817276423-A
Country	US
Kind code	B2
Filing date	Sep 18, 2018
Priority date	Sep 18, 2018
Publication date	Aug 6, 2024
Grant date	Aug 6, 2024

Abstract

A display device includes a gate electrode, a gate insulating film, a first metal oxide layer having crystallinity, and a second metal oxide layer having non-crystallinity. The first metal oxide layer and the second metal oxide layer are sequentially laminated on a substrate. The first metal oxide layer and the second metal oxide layer are in contact with each other in all regions where the first metal oxide layer and the second metal oxide layer overlap each other. The first metal oxide layer at least partially has a first semiconductor region serving as a semiconductor. One of the first metal oxide layer and the second metal oxide layer at least partially has a conductor region made electrically conductive.

First claim

The invention claimed is:

1. A display device comprising:
at least one transistor,
wherein the at least one transistor has a configuration including a gate electrode, a gate insulating film, a first metal oxide layer having crystallinity, and a second metal oxide layer having non-crystallinity,
the first metal oxide layer and the second metal oxide layer are laminated on a substrate in this order,
the first metal oxide layer and the second metal oxide layer are in contact with each other in all regions where the first metal oxide layer and the second metal oxide layer overlap each other,
the first metal oxide layer, at least partially, has a first semiconductor region serving as a semiconductor,
one of the first metal oxide layer and the second metal oxide layer, at least partially, has a conductor region made electrically conductive,
the second metal oxide layer, at least partially, has a second semiconductor region serving as a second semiconductor,
the first metal oxide layer has the conductor region,
the first semiconductor region is divided into a source region side and a drain region side so as to be paired with the conductor region in the first metal oxide layer, and
at least a part of the second semiconductor region is sandwiched between the first semiconductor region on the source region side and the first semiconductor region on the drain region side.

2. The display device according to claim 1 ,
wherein the first metal oxide layer is formed of a ternary oxide semiconductor containing at least tungsten or tin.

3. The display device according to claim 1 ,
wherein the second metal oxide layer is formed of a ternary oxide semiconductor containing at least tungsten or tin.

4. The display device according to claim 1 ,
wherein the first metal oxide layer and the second metal oxide layer are formed of an identical material.

5. The display device according to claim 1 ,
wherein an edge between the conductor region and the first semiconductor region in the first metal oxide layer matches an edge of the second metal oxide layer.

6. The display device according to claim 1 ,
wherein the second metal oxide layer has the conductor region, and
an edge between the conductor region and the first semiconductor region in the first metal oxide layer matches an edge of the conductor region and the second semiconductor region in the second metal oxide layer.

7. The display device according to claim 1 ,
wherein the first metal oxide layer is sandwiched between the substrate and the gate electrode, and
the first semiconductor region has a shape matching the gate electrode.

8. The display device according to claim 7 ,
wherein the second semiconductor region has a shape matching the gate electrode.

9. The display device according to claim 1 ,
wherein the gate electrode is sandwiched between the substrate and the first metal oxide layer, and
in a channel length direction in which a source region and a drain region face each other, a width of the gate electrode is larger than a width of the first semiconductor region or the second semiconductor region.

10. The display device according to claim 1 , further comprising:
an interlayer insulating film and a terminal electrode laminated on the second metal oxide layer,
wherein the terminal electrode is electrically connected to the conductor region through a contact hole formed in the interlayer insulating film.

11. A display device comprising:
at least one transistor,
wherein the at least one transistor has a configuration including a gate electrode, a gate insulating film, a first metal oxide layer having crystallinity, and a second metal oxide layer having non-crystallinity,
the first metal oxide layer and the second metal oxide layer are laminated on a substrate in this order,
the first metal oxide layer and the second metal oxide layer are in contact with each other in all regions where the first metal oxide layer and the second metal oxide layer overlap each other,
the first metal oxide layer, at least partially, has a first semiconductor region serving as a semiconductor,
one of the first metal oxide layer and the second metal oxide layer, at least partially, has a conductor region made electrically conductive,
the second metal oxide layer, at least partially, has a second semiconductor region serving as a second semiconductor,
the at least one transistor comprises a first transistor and a second transistor provided on the substrate,
in the first transistor, the second semiconductor region is divided into a first source region side and a first drain region side,
the first semiconductor region is positioned between the divided second semiconductor regions serves as a channel region,
in the second transistor, the first semiconductor region is divided into a second source region side and a second drain region side, and
the second semiconductor region is positioned between the divided first semiconductor regions serves as a channel region.

12. The display device according to claim 11 ,
wherein the first transistor serves as a write transistor, and
the second transistor serves as a drive transistor.

13. The display device according to claim 12 ,
wherein the second transistor further serves as an initialization transistor configured to initialize a voltage of the drive transistor, and
the second transistor further serves as a threshold voltage compensation transistor configured to compensate for a threshold voltage of the drive transistor.

14. The display device according to claim 11 ,
wherein the first metal oxide layer is formed of a ternary oxide semiconductor containing at least tungsten or tin.

15. The display device according to claim 11 ,
wherein the second metal oxide layer is formed of a ternary oxide semiconductor containing at least tungsten or tin.

16. The display device according to claim 11 ,
wherein the first metal oxide layer and the second metal oxide layer are formed of an identical material.

17. The display device according to claim 11 ,
wherein the first metal oxide layer is sandwiched between the substrate and the gate electrode, and
the first semiconductor region has a shape matching the gate electrode.

18. The display device according to claim 17 ,
wherein the second semiconductor region has a shape matching the gate electrode.

19. The display device according to claim 11 ,
wherein the gate electrode is sandwiched between the substrate and the first metal oxide layer, and
in a channel length direction in which a source region and a drain region face each other, a width of the gate electrode is larger than a width of the first semiconductor region or the second semiconductor region.

20. The display device according to claim 11 , further comprising:
an interlayer insulating film and a terminal electrode laminated on the second metal oxide layer,
wherein the terminal electrode is electrically connected to the conductor region through a contact hole formed in the interlayer insulating film.

Assignees

• Sharp Kk

Inventors

• ITO Kazuatsu

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title