Energy harvest and storage device for semiconductor chips and methods for forming the same

Patent metadata

Field	Value
Publication number	US-12057516-B2
Application number	US-202217730392-A
Country	US
Kind code	B2
Filing date	Apr 27, 2022
Priority date	Apr 27, 2022
Publication date	Aug 6, 2024
Grant date	Aug 6, 2024

Abstract

A semiconductor structure may include semiconductor devices located on a substrate, metal interconnect structures that are located within dielectric material layers overlying the semiconductor devices and are electrically connected to the semiconductor devices, and an energy harvesting device located over the metal interconnect structures and comprising a Schottky barrier diode, a first diode electrode located on a first side of the Schottky barrier diode, and a second diode electrode connected to a second side of the Schottky barrier diode.

First claim

What is claimed is:

1. A semiconductor structure comprising:
semiconductor devices located on a substrate;
metal interconnect structures that are located within dielectric material layers overlying the semiconductor devices and are electrically connected to the semiconductor devices;
an energy harvesting device located over the metal interconnect structures and comprising a Schottky barrier diode, wherein the Schottky barrier diode comprises a first diode electrode located on a first side of the Schottky barrier diode, and a second diode electrode connected to a second side of the Schottky barrier diode; and
a battery structure overlying the metal interconnect structures and comprising:
an energy storage medium;
a first battery electrode that is the second diode electrode of the Schottky barrier diode; and
a second battery electrode.

2. The semiconductor structure of claim 1 , wherein:
the first diode electrode of the Schottky barrier diode is electrically connected to a first metal interconnect structure selected from the metal interconnect structures; and
the second battery electrode of the battery structure is electrically connected to a second metal interconnect structure selected from the metal interconnect structures.

3. The semiconductor structure of claim 1 , wherein the energy storage medium comprises an ionic crystal plate including an ionic crystal having ionic conductivity greater than 1.0×10 −5 S/cm in a temperature range from −40 degrees Celsius to 125 degrees Celsius.

4. The semiconductor structure of claim 3 , wherein the battery structure comprises a blocking dielectric layer comprising a dielectric metal oxide material and located between the ionic crystal plate and the first diode electrode.

5. The semiconductor structure of claim 4 , wherein the battery structure comprises conductive metal oxide layer located between the blocking dielectric layer and the first battery electrode.

6. The semiconductor structure of claim 1 , wherein the first battery electrode comprises a metallic material including at least one transition metal or a conductive metal oxide material.

7. The semiconductor structure of claim 1 , wherein the Schottky barrier diode comprises a Schottky barrier junction located at an interface between a high work function plate including a high work function material having a work function greater than 4.5 eV and a compound semiconductor material plate including a compound semiconductor material.

8. The semiconductor structure of claim 7 , wherein the compound semiconductor material has a band gap energy in a range from 0.1 eV to 0.35 eV.

9. The semiconductor structure of claim 8 , wherein:
the high work function material comprises a material selected from a transparent conductive oxide, ruthenium, rhodium, cobalt, gold, palladium, nickel, iridium, or platinum; and
the compound semiconductor material comprises a material selected from indium antimonide, indium arsenide, lead telluride, or bismuth telluride.

10. A semiconductor structure comprising:
an energy harvesting device comprising:
a Schottky barrier diode;
a first diode electrode located on a first side of the Schottky barrier diode; and
a second diode electrode connected to a second side of the Schottky barrier diode; and

a battery structure underlying the energy harvesting device and comprising:
an energy storage medium;
a first battery electrode that is the second diode electrode of the Schottky barrier diode; and
a second battery electrode,

wherein the semiconductor structure further comprises:
semiconductor devices located on a substrate; and
metal interconnect structures that are located within dielectric material layers overlying the semiconductor devices and electrically connecting the first diode electrode to a first node of the semiconductor devices and the second battery electrode to a second node of the semiconductor devices.

11. The semiconductor structure of claim 10 , wherein the energy harvesting device and the energy storage medium have a same shape and a same size in a plan view along a vertical direction.

12. The semiconductor structure of claim 10 , wherein:
the Schottky barrier diode comprises a Schottky barrier junction located at an interface between a high work function plate including a high work function material having a work function greater than 4.5 eV and a compound semiconductor material plate including a compound semiconductor material; and
the high work function plate has openings therethrough and the compound semiconductor material plate has a greater area than the high work function plate.

13. The semiconductor structure of claim 10 , wherein:
the Schottky barrier diode comprises a Schottky barrier junction located at an interface between a high work function plate including a high work function material having a work function greater than 4.5 eV and a compound semiconductor material plate including a compound semiconductor material; and
the Schottky barrier junction has a vertical undulation in a vertical cross-sectional profile such that raised portions of the Schottky barrier junction are interlaced with recessed portions of the Schottky barrier junction.

14. The semiconductor structure of claim 11 , wherein the energy storage medium comprises an ionic crystal plate including an ionic crystal having ionic conductivity greater than 1.0×10 −5 S/cm in a temperature range from −40 degrees Celsius to 125 degrees Celsius.

15. The semiconductor structure of claim 14 , wherein the battery structure comprises a blocking dielectric layer comprising a dielectric metal oxide material and located between the ionic crystal plate and the first diode electrode.

16. A method of forming a semiconductor structure, the method comprising:
forming semiconductor devices on a substrate;
forming metal interconnect structures and dielectric material layers over the semiconductor devices, wherein the metal interconnect structures are electrically connected to the semiconductor devices, and are formed in the dielectric material layers;
forming a battery structure over the metal interconnect structures, wherein the battery structure comprises an energy storage medium, a first battery electrode that is the second diode electrode of the Schottky barrier diode, and a second battery electrode; and
forming an energy harvesting device over the metal interconnect structures and over the battery structure, wherein the energy harvesting device comprises a Schottky barrier diode, a first diode electrode located on a first side of the Schottky barrier diode, and a second diode electrode connected to a second side of the Schottky barrier diode.

17. The method of claim 16 , wherein:
the second battery electrode is formed on one of the metal interconnect structures; and
the method further comprises forming additional metal interconnect structures electrically connecting the first diode electrode to one of the metal interconnect structures.

18. The method of claim 16 , wherein the energy storage medium is formed by depositing and patterning an ionic crystal having ionic conductivity greater than 1.0×10 −5 S/cm in a temperature range from −40 degrees Celsius to 125 degrees Celsius.

19. The method of claim 16 , wherein:
the Schottky barrier diode is formed by depositing and patterning a layer stack that includes a compound semiconductor material layer and a high work function material layer;
the high work function material layer comprises high work function material having a work function greater than 4.5 eV;

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Li fu-hai
• Ong Yi Ching
• Huang Kuo-Ching

Classifications

• H10F77/90 Primary

  Energy storage means directly associated or integrated with photovoltaic cells, e.g. capacitors integrated with photovoltaic cells · CPC title

• H10F71/00

  Manufacture or treatment of devices covered by this subclass (patterning processes to connect thin photovoltaic cells in integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/33; manufacture or treatment of encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/80; manufacture or treatment of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) · CPC title

• H10F10/18 Primary

  Photovoltaic cells having only Schottky potential barriers · CPC title

• H10F19/50

  Integrated devices comprising at least one photovoltaic cell and other types of semiconductor or solid-state components (H10F19/75 takes precedence) · CPC title

• H01L31/18

  Electricity · mapped topic