Thin film transistor array panel

Patent metadata

Field	Value
Publication number	US-12057509-B2
Application number	US-202117544353-A
Country	US
Kind code	B2
Filing date	Dec 7, 2021
Priority date	Mar 22, 2018
Publication date	Aug 6, 2024
Grant date	Aug 6, 2024

Abstract

A thin film transistor array panel includes a substrate, a first gate electrode on the substrate, a semiconductor layer on the first gate electrode, the semiconductor layer including a drain region, a source region, a lightly doped drain (LDD) region, and a channel region, a second gate electrode on the semiconductor layer, the first gate electrode and the second gate electrode each overlapping the channel region, a control gate electrode that overlaps the LDD region, and a source electrode and a drain electrode respectively connected with the source region and the drain region of the semiconductor layer.

First claim

What is claimed is:

1. A thin film transistor array panel, comprising:
a substrate;
a gate electrode on the substrate;
a first control gate electrode and a second control gate electrode on a same layer as the gate electrode, the first control gate electrode and the second control gate electrode being respectively disposed at one side and the other side of the gate electrode, the first control gate electrode and the second control gate electrode being physically separated from, and disposed at a distance from, the gate electrode such that a voltage to the first control gate electrode and a voltage to the second control gate electrode can be independently applied from a voltage applied to the gate electrode;
a semiconductor layer disposed above the gate electrode, the first control gate electrode, and the second control gate electrode, the semiconductor layer including a channel that overlaps the gate electrode, a drain region, a source region, a first lightly doped drain region that is disposed between the channel and the drain region and overlaps the first control gate electrode, and a second lightly doped drain region that is disposed between the channel and the source region and overlaps the second control gate electrode; and
a source electrode and a drain electrode respectively connected with the source region and the drain region, wherein
the gate electrode overlaps the first control gate electrode and the second control gate electrode in a direction parallel to one surface of the substrate.

2. The thin film transistor array panel as claimed in claim 1 , further comprising:
a first insulation layer between the gate electrode and the semiconductor layer; and
a second insulation layer on the semiconductor layer.

3. The thin film transistor array panel as claimed in claim 1 , further comprising:
a first insulation layer between the semiconductor layer and the gate electrode; and
a second insulation layer on the gate electrode.

4. The thin film transistor array panel as claimed in claim 1 , wherein the source region and the drain region of the semiconductor layer are doped with a P-type impurity.

5. The thin film transistor array panel as claimed in claim 4 , wherein
the first control gate electrode is a drain control gate electrode and the second control gate electrode is a source control gate electrode, and
in response to a voltage applied to the gate electrode being higher than a predetermined voltage, the drain control gate electrode and the source control gate electrode are each applied with a positive voltage independent of the voltage applied to the gate electrode.

6. The thin film transistor array panel as claimed in claim 5 , wherein
in response to a voltage applied to the gate electrode being lower than a predetermined voltage, the drain control gate electrode and the source control gate electrode are each applied with a negative voltage independent of the voltage applied to the gate electrode.

7. A thin film transistor array panel, comprising:
a substrate;
a gate electrode on and over the substrate;
a semiconductor layer disposed on and over the gate electrode, the semiconductor layer including a source region, a drain region, and a channel region;
a control gate electrode on and over the semiconductor layer and disposed farther from the substrate than the semiconductor layer, no portion of the control gate electrode overlapping the gate electrode;
a source electrode and a drain electrode connected with the semiconductor layer, and
a pixel electrode on and over the source electrode.

8. The thin film transistor array panel as claimed in claim 7 , further comprising:
a first insulation layer between the gate electrode and the semiconductor layer; and
a second insulation layer between the semiconductor layer and the control gate electrode.

9. The thin film transistor array panel as claimed in claim 7 , wherein
in response to a voltage applied to the gate electrode being higher than a predetermined voltage, the control gate electrode is applied with a positive voltage.

10. The thin film transistor array panel as claimed in claim 9 , wherein
in response to a voltage applied to the gate electrode being lower than a predetermined voltage, the control gate electrode is applied with a negative voltage.

11. The thin film transistor array panel as claimed in claim 7 , wherein the control gate electrode is physically separated from the gate electrode such that a voltage to the control gate electrode can be independently applied from a voltage applied to the gate electrode.

12. The thin film transistor array panel as claimed in claim 7 , wherein the gate electrode overlaps a center of the channel.

13. The thin film transistor array panel as claimed in claim 1 , wherein the gate electrode overlaps a center of the channel.

14. The thin film transistor array panel as claimed in claim 7 , wherein the control gate electrode overlaps a lightly doped drain region of the semiconductor layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Do Hyung
• Kim Gun Hee
• Kim Hyeon Sik
• Park Sang Ho
• Jeon Joo Hee

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D30/6733

  Multi-gate TFTs · CPC title

• H10D30/6704

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title