SPAD pixel

Patent metadata

Field	Value
Publication number	US-12057461-B2
Application number	US-202318225298-A
Country	US
Kind code	B2
Filing date	Jul 24, 2023
Priority date	Oct 12, 2020
Publication date	Aug 6, 2024
Grant date	Aug 6, 2024

Abstract

An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.

First claim

The invention claimed is:

1. A method of manufacturing a multi-level electronic device, comprising:
forming a first level including a SPAD in a first semiconductor layer;
molecular bonding a stack of layers to said first level, said stack of layers including a second semiconductor layer;
processing said second semiconductor layer to form transistor devices for a quench circuit of a second level;
covering the transistor devices of the quench circuit with a first insulating layer;
forming a third level including a processing circuit in a third semiconductor layer; and
hybrid bonding the third level to the first insulating layer of the second level.

2. The method of claim 1 , wherein covering the transistor devices of the quench circuit with the first insulating layer further comprises forming first metal pads, wherein forming the third level comprises forming second metal pads in a second insulating layer, and where hybrid bonding comprises bonding the first and second insulating layers to each other and bonding the first and second metal pads to each other.

3. The method of claim 1 , wherein processing said second semiconductor layer to form transistor devices comprises etching the second semiconductor layer to form a plurality of distinct semiconductor regions and providing at least one transistor device in each distinct semiconductor region.

4. The method of claim 1 , wherein forming the first level comprises forming a third insulating layer covering the SPAD, wherein said stack of layers includes a fourth insulating layer, and wherein molecular bonding comprises bonding the third and fourth insulating layers to each other.

5. The method of claim 1 , wherein the stack of layers comprises an SOI structure including a fifth insulating layer between the second semiconductor layer and a semiconductor support, the method further comprising, before processing said second semiconductor layer, removing the fifth insulating layer and the semiconductor support.

6. A method of manufacturing a multi-level electronic device, comprising:
a) forming a first level including a first semiconductor layer and a first insulating layer;
b) forming a stack of layers of a second level including a second semiconductor layer and a second insulating layer;
c) bonding by molecular bonding the second insulating layer of said stack of layers to the first insulating layer;
d) forming a first interconnection layer including first pads over the second semiconductor layer;
e) forming a stack of layers of a third level including a third semiconductor layer and a second interconnection layer including second pads; and
f) bonding by hybrid bonding the first and second interconnection layers and first and second pads.

7. The method of claim 6 , wherein forming the first level comprises forming a SPAD in the first semiconductor layer, the method further comprising forming transistors for a quench circuit in the second semiconductor layer, and electrically connecting the quench circuit to the SPAD using vias passing through the molecularly bonded first and second insulating layers.

8. The method of claim 7 , further comprising forming transistors for a processing circuit in the third semiconductor layer and wherein the first and second pads electrically connect the processing circuit to the quench circuit.

9. The method of claim 6 , wherein the stack of layers of the second level comprises an SOI structure including a third insulating layer between the second semiconductor layer and a semiconductor support, the method further comprising, before forming the first interconnection layer, removing the third insulating layer and the semiconductor support.

10. An electronic device, comprising:
a stack including a first level with a first semiconductor layer including a SPAD, a second level with a second semiconductor layer, different from the first semiconductor layer, including a quench circuit for said SPAD, and a third level with a third semiconductor layer, different from the first and second semiconductor layers, including a circuit for processing data generated by said SPAD;
wherein the first level is bonded to the second level by molecular bonding and wherein the second level is bonded to the third level by hybrid bonding.

11. The device according to claim 10 , wherein the first level comprises a single SPAD.

12. The device according to claim 10 , wherein the first level comprises no electronic component other than the SPAD.

13. The device according to claim 10 , wherein the second level only comprises said quench circuit.

Assignees

• St Microelectronics Crolles 2 Sas
• St Microelectronics Res & Dev Ltd

Inventors

• Guyader Francois
• Pellegrini Sara
• Rae Bruce

Classifications

• H10F39/809 Primary

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• H10F39/811

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